Method for fabricating a semiconductor device having a planar surface
AssigneeMotorola, Inc.
InventorStephen S. Poon
Life of this patent
Estimating the term…
Abstract
A planar surface (24) is obtained in a semiconductor device (10) having regions of differing material composition by means of a non-selective planarization process. The non-selective planarization process removes insulating material and conductive material at substantially the same rate. In one embodiment of the invention, stud vias (22) are formed by the removal of portions of a conductive layer (20) overlying the surface of an interlevel dielectric layer (16). Once the conductive layer (20) has been removed, the planarization process is continued and surface portions of the interlevel dielectric layer (16) are also removed. Upon completion of the process a planar surface (24) is formed having regions of conductive material and insulating material.
Claims12
A method for fabricating a semiconductor device comprising the steps of:
- providing a substrate having a patterned first conductive layer thereon;
- forming an insulating layer overlying the first conductive layer;
- forming an opening in the insulating layer exposing a portion of the first conductive layer;
- forming a second conductive layer overlying the insulating layer and within the opening;
- and
- simultaneously removing the second conductive layer that lies over the insulating layer and removing a surface portion of the insulating layer to form a planar surface,
- wherein the step of simultaneous removal is performed such that the removal rates of the second conductive layer and the insulating layer are substantially the same, and
- wherein the step of simultaneous removal is carried out by chemical-mechanical polishing using a non-selective slurry comprising aluminum nitride and alumina particles suspended in deionized water.
A method for fabricating a semiconductor device comprising the steps of:
- providing a substrate having patterned first and second conductive layers formed sequentially over the substrate, wherein the first and second conductive layers are separated by an interlevel dielectric layer and the second conductive layer lies over the interlevel dielectric layer;
- forming a planarizing layer overlying the second conductive layer;
- forming openings in the planarizing layer and the interlevel dielectric layer exposing a portion of the second conductive layer and a portion of the first conductive layer;
- forming a metal layer overlying the planarizing layer and within the openings;
- selectively removing a first surface portion of the metal layer;
- and
- simultaneously removing a second surface portion of the metal layer and a surface portion of the planarizing layer to form a planar surface,
- wherein the simultaneous removal is carried out by chemical-mechanical polishing using a non-selective slurry comprising aluminum nitride and alumina particles suspended in deionized water.
A method for fabricating a semiconductor device comprising the steps of:
- providing a substrate having a patterned first conductive layer thereon;
- forming an insulating layer overlying the first conductive layer;
- forming an opening in the insulating layer exposing a portion of the first conductive layer;
- forming a second conductive layer on the insulating layer and within the opening;
- placing the substrate in a polishing apparatus having a non-selective, water-based slurry containing aluminum nitride, alumina, and silica;
- and
- polishing the second conductive layer and a surface portion of the insulating layer to form a planar surface, wherein the polishing removes the conductive layer and the insulating layer at substantially the same rate.
Dependencies are inferred from the claim text.