1X asynchronous data sampling clock
OwnerFrank Marinaroinventor
Life of this patent
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Abstract
A circuit for retiming asynchronous data. A sampling clock is derived in which the system clock frequencies are no higher than that of the data frequency. The leading edge of the signal from a received data-to-clock position circuit and a bias distortion circuit are combined and decoded to determine the center of the received data to select the proper sampling clock for the received data.
Claims19
A received data sampling clock circuit for use in asynchronous local area networks, comprising a RD (received data)-to-clock position circuit for determining the position of RD with respect to a system clock;
- a bias distortion circuit for determining the pulse width of the RD;
- and means for combining and decoding output signals from said RD-to-clock position circuit and said bias distortion circuit for determining an approximate center of said RD and for selecting a proper sampling clock for said RD.
A method for receiving and retiming asynchronous data, comprising:
- transferring received data to an RD-to-clock position circuit to determine a delayed clock-to-RD phase relationship;
- compensating for bias distortion associated with said received data by providing a bias distortion circuit;
- and
- combining and decoding outputs from said RD-to-clock position circuit and said bias distortion circuit to determine a true center of said received data and to select a proper sampling clock for said received data.
Dependencies are inferred from the claim text.