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US 5,327,378 AGranted
Easily manufacturable compact EPROM
AssigneeWaferScale Integration, Inc.
InventorReza Kazerounian
Life of this patent
Estimating the term…
Abstract
An EPROM array comprises a plurality of floating gate memory cell transistors and a multiplicity of floating gate select transistors arranged so that at least one select transistor controls the current to a group of floating gate memory cell transistors. Each floating gate select transistor remains unprogrammed or substantially unprogrammed even though the floating gate memory cell transistors in the memory array are selectively programmed to store information. The use of floating gate transistors for both memory cell transistors and select transistors simplifies the manufacturing process and improves yield.
Claims23
An electrically programmable read only memory containing an array of floating gate transistors, said array comprising:
- a virtual source;
- a first group and a second group of floating gate transistors, wherein each floating gate transistor in said first and second groups comprises:
- a drain region and a channel region formed between said drain region and said virtual source;
- and
- a floating gate formed over the channel region between said virtual source and said drain region, said floating gate being separated by a dielectric material from said channel region;
- at least one first select transistor connected between said virtual source and a first bit line which functions as a drain for said first group of floating gate transistors, but as a source for said second group of floating gate transistors;
- and
- at least one second select transistor connected between said virtual source and a second bit line which functions as a drain for said second group of floating gate transistors, but as a source for said first group of floating gate transistors,
- said first and said second select transistors being arranged so that said at least one second select transistor acts as the control transistor for each of the transistors in said first group of floating gate transistors in said array, and said at least one first select transistor acts as the control transistor for each of the transistors in said second group of floating gate transistors in said array, and said at least one first select transistor and said at least second select transistor comprise unprogrammed or substantially unprogrammed floating gate transistors.
6 more elements
An array of floating gate transistors for use in an electrically programmable read only memory, said array comprising:
- a plurality of floating gate transistors wherein each floating gate transistor comprises:
- a virtual source region, a drain region and a channel region formed therebetween;
- and
- a floating gate formed over the channel region between said source region and said drain region, said floating gate being separated by a dielectric material from said channel region;
- and
- at least one first select transistor comprising an unprogrammed or substantially unprogrammed floating gate transistor connected between the virtual source region of each of said plurality of floating gate transistors and a separate bit line which functions as a source for said plurality of floating gate transistors.
3 more elements
An array of floating gate transistors for use in an EPROM wherein:
- each floating gate transistor comprises:
- a source region, a drain region and a channel therebetween;
- and
- a floating gate placed over and insulated from said channel region;
- and
- at least one select transistor connected between a source bit-line and the sources of each of a plurality of floating gate transistors, said at least one select transistor being an unprogrammed or substantially unprogrammed floating gate transistor and being capable of controlling the current to each of said plurality of floating gate transistors.
3 more elements
An EPROM array comprising:
- a multiplicity of floating gate transistors arranged in rows and columns, said floating gate transistors being arranged such that the floating gate transistors in each column are divided into M groups of N floating gate transistors each, where M and N are each selected integers;
- a virtual ground source bit-line divided into M segments formed between the floating gate transistors in the c.sup.th and the (c+1).sup.th columns, where c is an odd integer 1, 3, . . . C given by 1.ltoreq.c.ltoreq.(C+1)) and (C+1) is the maximum number of columns in the array, wherein each of said segments comprises a virtual source;
- at least one first transfer transistor comprising at least one unprogrammed floating gate transistor connecting one segment comprising a virtual source to a first metal bit-line, said first metal bit-line functioning as a source for the N floating gate transistors in the (c+1).sup.th column connected to said one segment;
- and
- at least one second transfer transistor comprising at least one unprogrammed or substantially unprogrammed floating gate transistor connecting said one segment comprising a virtual source to a second metal bit-line, said second metal bit-line functioning as a source for the N floating gate transistors in the c.sup.th column connected to said one segment.
2 more elements
An EPROM array comprising:
- a plurality of P floating gate transistors, where P equals the total number of floating gate transistors in the array;
- and
- a multiplicity of M select transistors, each select transistor comprising an unprogrammed floating gate transistor, where M equals the total number of select transistors in the array and is less than P, said select transistors being arranged in the array such that one select transistor controls the current to each floating gate transistor.
Dependencies are inferred from the claim text.