US 5,327,003 AGranted

Semiconductor static RAM having thin film transistor gate connection

AssigneeFujitsu Limited

InventorsKazuo Itabashi, Taiji Ema

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Abstract

A semiconductor memory device includes a semiconductor substrate, a memory cell provided on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, where each of the first and second transfer transistors, the first and second driver transistors and the first and second thin film transistor loads have a source, a drain and a gate electrode, and a connecting region in which the drain of the second thin film transistor load, the gate electrode of the first thin film transistor load and the gate electrode of the first driver transistor are connected. The gate electrode of the first driver transistor, the gate electrode of the first thin film transistor load and the drain of the second thin film transistor load are made of conductor layers which are stacked on the semiconductor substrate with an insulator layer interposed between the conductor layers, and a top one of the stacked conductor layers makes contact with a top surface of a bottom one of the stacked conductor layers and with side surfaces of each conductor layer provided between the top and bottom conductor layers within the connecting region.

Claims21

Dependent claims

A semiconductor memory device comprising:

a semiconductor substrate;
a memory cell provided on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, each of said first and second transfer transistors, said first and second driver transistors and said first and second thin film transistor loads having a source, a drain and a gate electrode;
a connection region in which the drain of the second thin film transistor load, the gate electrode of the first thin film transistor load and the gate electrode of the first driver transistor are electrically connected;
the gate electrode of the first driver transistor, the gate electrode of the first thin film transistor load and the drain of the second thin film transistor load being made of conductor layers which are stacked in succession on said semiconductor substrate, a respective insulator layer being interposed between each two successively stacked conductor layers and thereby defining a bottom conductor layer and successive, intermediate and top conductor layers with respective insulation layers interposed therebetween;
and
a surface portion of the bottom conductor layer being exposed in the connecting region and at least transverse wall surfaces of each intermediate conductor layer being exposed within the connecting region and the top conductor layer being connected electrically within, and by, the connecting region with the exposed top surface portion of the bottom stacked conductor layer and primarily with the respective transverse wall surfaces of the intermediate, stacked conductor layers.

3 more elements

A semiconductor memory device comprising:

a semiconductor substrate;
a memory cell provided on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, each of said first and second transfer transistors, said first and second driver transistors and said first and second thin film transistor loads having a source, a drain and a gate electrode;
a connection region in which the drain of the second thin film transistor load, the gate electrode of the first thin film transistor load and the gate electrode of the first driver transistor are electrically connected;
the gate electrode of the first driver transistor, the gate electrode of the first thin film transistor load and the drain of the second thin film transistor load being made of conductor layers which are stacked in succession on said semiconductor substrate and a respective insulator layer is interposed between each two successive stacked conductor layers and thereby defining a bottom conductor layer and successive, intermediate and top conductor layers with respective insulation layers interposed therebetween;
and
the connecting region further comprising:
a contact window extending through the successively stacked top and intermediate conductor layers and each interposed insulator layer and exposing a surface portion of the bottom conductor layer, respective transverse wall surfaces of the stacked conductor layers and interposed insulator layers being exposed at and defining corresponding sidewalls of the contact hole, the respective transverse wall surfaces of the stacked conductor layers and the interposed insulator layers, corresponding to each sidewall of the contact hole, being substantially aligned, and
a conductor material formed within and covering at least the sidewalls of the contact window and the exposed top surface portion of the bottom conductor layer, the conductor material being formed on at least the exposed transverse wall surfaces of the respective conductor layers and electrically connecting the top conductor layer with the intermediate conductor layers and the bottom layer.

5 more elements

Dependencies are inferred from the claim text.