US 5,326,998 A · Semiconductor memory cell and manufacturing method thereof

Abstract

A semiconductor memory cell and device having a tubular formed storage electrode of a capacitor through which a bit line passes. The source, gate and drain of a switching transistor are arranged in a direction parallel to a longitudinal axis of the tubular storage electrode. An active region also is arranged in a parallel or superposing direction relative to the bit line and in a perpendicular direction relative to the word line. A manufacturing method thereof includes forming a switching transistor, forming a part of the capacitor storage electrode connected with the drain of the switching transistor, forming an oxide film side wall, forming a bit line in parallel to a longitudinal axis of the active region, forming a capacitor storage electrode of tubular form, covering the surface of the capacitor storage electrode with a capacitor dielectric film, and forming a plate electrode of the capacitor thereon.

Claims17

Dependent claims

A semiconductor memory device, comprising:

a plurality of switching transistors each having a gate and source and drain regions formed in an active region of a semiconductor substrate;
word lines coupled to the gates of the switching transistors through an insulating layer;
bit lines coupled to the source regions of the switching transistors;
tubular storage electrodes coupled to the drain regions of the switching transistors, each tubular storage electrode having an interior region, wherein a bit line passes through the interior regions of the tubular storage electrodes;
a dielectric layer on the tubular storage electrodes;
and
a plate electrode on the dielectric layer.

4 more elements

A method for manufacturing a semiconductor memory cell comprising:

(1) forming a switching transistor with a gate, source and drain in an active region in a semiconductor substrate, with the active region defined by a field oxide film that electrically isolates the active region;
(2) forming a first element of a capacitor storage electrode connected to the drain of the switching transistor by depositing a first oxide film, opening a buried contact in the first oxide film, depositing a first polysilicon film on the overall surface, depositing a second oxide film, and patterning the second oxide film and the first polysilicon film perpendicular to the longitudinal axis of the active region;
(3) forming an oxide film side wall beside the first polysilicon film by depositing an oxide film on the overall surface and etching back the oxide film;
(4) forming a bit line by opening a bit line contact, depositing a second polysilicon film, etching back the second polysilicon film, depositing a refractory metal film on the second polysilicon film, depositing a third oxide film, and patterning the third oxide film, the refractory metal film, and the second polysilicon film parallel to the longitudinal axis of the active region;
(5) depositing a first isolation film of a material with greater etching selectivity than the second oxide film, the first polysilicon film and a third polysilicon film, patterning the first isolation film to cover the bit line in a parallel manner, depositing the third polysilicon film and a second isolation film of a material with greater etching selectivity than the second oxide film and the first and third polysilicon films, and patterning the second isolation film so as to cover the bit line in a parallel manner;
(6) etching the third polysilicon film, the second oxide film, and the first polysilicon film in turn by using the second isolation film as a mask layer and thereby forming an upper element of the capacitor storage electrode;
(7) forming a storage electrode of the capacitor by depositing a fourth polysilicon film, dry etching the fourth polysilicon film and then removing the second isolation film, thereby forming a side wall projection connecting the third polysilicon film above the bit line and the first polysilicon film under the bit line;
and
(8) forming a dielectric film of the capacitor and a plate electrode of the capacitor on the surface of the storage electrode of the capacitor.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor memory cell and manufacturing method thereof

Life of this patent

Semiconductor memory cell and manufacturing method thereof

Life of this patent

Abstract

Claims17