Protective circuit for protecting contacts of monolithic integrated circuits by preventing parasitic latch up with other integrated circuit elements

In a monolithic integrated circuit defined in a substrate (Sb) including a plurality of circuit elements, a connecting contact (A), and a first and second supply terminal (VSS, VDD), a protective circuit for protecting the connecting contacts from electrostatic discharges by means of resistive and sink devices for electrostatic discharges comprising:

• at least one four-layer device (thyristor) (ta, ts) with defined switching threshold and a low-resistivity sink path (sa) from the connecting contact (A) to at least one of the first and second supply terminals (VSS, VDD) proximate to each connecting contact (A);
• and
• means (zw2, z5) for preventing substantial flow of current (i3, i4) between at least portions of the four-layer device (ta, ts) and at least one of said plurality of circuit elements (t2'), said plurality circuit elements (t2') forming four-layer devices (ta, t2') with said portions of the four-layer device (ta);
• wherein the four-layer device (ta, ts) contains at least one three-layer devices (ts) comprising the substrate (Sb), a semiconductor region (z4) formed in the substrate as a well (W1), and a semiconductor region (z3) disposed in the well, with the conductivity types of the successive layers (Sb, z4, z3) of the three-layer device being opposite to each other, and the substrate (Sb) being of a first conductivity type;
• and
• wherein the four-layer device (ta, ts) is formed in a first and second semiconductor zone (H1, H2) by means of regions formed into a surface of the substrate, and contains in the first semiconductor zone (H1), in a lateral configuration, a first and second region (z1, z2) of a second conductivity type separated by a substrate wall (st);
• wherein the protective circuit further comprises a contact area (a1) and a first and a second interconnection (f1, f2) connected to said contact area and having connected thereto drain terminals (D1, D2) of complementary CMOS output transistors (t1, t2) and wherein the first region (z1) provides a conductive connection at least between the connecting contact (A) and a contact area (a1) for the first and second interconnection (f1, f2);
• wherein the second region (z2) is connected to the first supply terminal (VSS);
• wherein the second semiconductor zone (H2) comprises a third region (z3) of the first conductivity type, a third interconnection (f3), and a fourth region (z4) of the second conductivity type, which forms a well (W1), the third region (z3) being coupled to the contact area (a1) by the third interconnection (f3) and disposed in the fourth region (z4) of the second conductivity type;
• and
• a lateral distance (s1) being defined between the first and second regions (z1, z2), a distance (s2) being defined between the first and second semiconductor zones (H1, H2), and lengths of the respective adjacent edge regions being defined so that after attainment of the turn-on threshold, the low-resistivity sink path (sa), which is controlled by the thyristor-like interaction of the first and second semiconductor zones, has at least one predetermined conductivity value, otherwise the turn-on threshold not being reached under normal operating conditions.