Semiconductor wafer level package
AssigneeMotorola, Inc.
InventorsVictor J. Adams, Paul T. Bennett, Henry G. Hughes, Brooks L. Scofield, Jr., Marilyn J. Stuckey
Life of this patent
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Abstract
A semiconductor wafer level package used to encapsulate a device fabricated on a semiconductor substrate wafer before dicing of the wafer into individual chips. A cap wafer is bonded to the semiconductor substrate wafer using a pre-patterned frit glass as a bonding agent such that the device is hermetically sealed inside a cavity. A hole in the cap wafer allows electrical connections to be made to the device through electrodes which pass through the frit glass seal.
Claims9
A semiconductor wafer level package, comprising:
- at least one device fabricated on a semiconductor substrate wafer and wherein the semiconductor substrate wafer has not been diced into a plurality of distinct chips;
- a cap wafer having a predetermined height and thickness with a predetermined pattern of frit glass walls deposited on a surface, the predetermined pattern being such that at least the device is completely surrounded by the frit glass walls;
- a hermetic seal produced by bonding the cap wafer to the semiconductor substrate wafer using the frit glass walls as a bonding agent such that the device is hermetically sealed in a cavity of predetermined dimensions formed by a combination of the semiconductor substrate wafer, the cap wafer, and the frit glass walls;
- and
- at least one electrode formed on the surface of the semiconductor substrate wafer which provides electrical coupling to the device fabricated on the semiconductor substrate wafer;
- and
- a hole fabricated in the cap wafer which provides access to a portion of the electrode from outside the cavity.
A semiconductor wafer level package, comprising:
- at least one device fabricated on a semiconductor substrate wafer and wherein the semiconductor substrate wafer has not been diced into a plurality of distinct chips;
- a cap wafer having a predetermined height and thickness with a predetermined pattern of frit glass walls deposited on a surface, the predetermined pattern being such that at least the device is completely surrounded by the frit glass walls;
- a hermetic seal produced by bonding the cap wafer to the semiconductor substrate wafer using the frit glass walls as a bonding agent such that the device is hermetically sealed in a cavity of predetermined dimensions formed by a combination of the semiconductor substrate wafer, the cap wafer, and the frit glass walls;
- and
- a controlled environment sealed within the cavity of predetermined dimensions which comprises an inert gas having a predetermined pressure which provides a predetermined mechanical damping of the device.
Dependencies are inferred from the claim text.