A mask read only memory device

A logic mask ROM, comprising:

• a semiconductor substrate having a plurality of diffusion regions of a given impurity adjacent to a contact region and a field oxide region and extending in a first direction said plurality of diffusion regions being separated and spaced-apart from each other by a first equidistance;
• a gate oxide layer disposed on the surface of said semiconductor substrate;
• a plurality of word lines positioned on the surface of said gate oxide layer extending in a second direction, said plurality of word lines being separated and spaced-apart by a second equidistance, each word line having a width substantially proportional to said first equidistance between adjacent diffusion regions, and each diffusion region having a width substantially proportional to said second equidistance between adjacent word lines;
• a first insulation layer disposed on selected word lines of said plurality of word lines, said first insulation layer having a thickness directly proportional to said second equidistance between adjacent word lines;
• a second insulation layer disposed to insulate said plurality of word lines;
• and
• a conduction layer positioned on the surface of said second insulation layer extending in said first direction perpendicular to said plurality of word lines and connected to the contact region of said semiconductor substrate.

A logic mask ROM, comprising:

• a semiconductor substrate;
• a gate oxide layer disposed on the surface of said semiconductor substrate;
• a plurality of word lines positioned on the surface of said gate oxide layer extending in a first direction, said plurality of word lines being separated and spaced-apart by an equidistance;
• a first insulation layer disposed on the surface of one of an odd number and an even number of word lines of said plurality of word lines, said first insulation layer having a thickness directly proportional to said equidistance between adjacent word lines;
• a second insulation layer for insulating said plurality of word lines;
• and
• a conduction layer positioned on the surface of said second insulation layer extending in a second direction perpendicular to said plurality of word lines and connected to the contact region of said semiconductor substrate.

A memory device, comprising:

• a semiconductor substrate of a first conductivity type;
• a plurality of bit lines disposed directly beneath the surface of said semiconductor substrate and formed by diffusion of impurities having a second conductivity type, said plurality of bit lines extending in a first direction;
• a first insulation layer disposed on the surface of said semiconductor substrate;
• a plurality of word lines positioned on the surface of said first insulation layer extending in a second direction perpendicular to said first direction, said plurality of word lines being separated ad spaced-apart by a give distance;
• and
• a second insulation layer disposed on the surface of selected word lines of said plurality of word lines, said second insulation layer having a thickness corresponding to said given distance between adjacent word lines.