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US 5,317,182 AGranted
Termination of the power stage of a monolithic semiconductor device
AssigneeConsorzio Per la Ricerca Sulla Microelectronica
InventorsRaffaele Zambrano, Antonio Grimaldi
Life of this patent
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Abstract
A smart power integrated circuit, in which the power stage includes a vertical-current-flow NMOS power transistor having many paralleled cells. A deeper P-type diffusion surrounds the P-type body region of the cells at the edge of the power stage. The junction between this deep P-type diffusion and the laterally adjacent N-type material has a lower curvature than the junction which would be formed by the P-type body region alone. This increases the transistor's breakdown voltage without degrading the transistor's on-state resistance R.sub.on.
Claims32
An integrated circuit device comprising:
- at least one monolithic body of semiconductor material, including a heavily doped N-type substrate and one or more epitaxial layers thereon, an outermost one of said epitaxial layers extending to a first surface of said monolithic body;
- a power stage and an integrated control circuit, said power stage containing one or more vertical-current-flow MOS transistors;
- said power stage including at least:
- a first patterned diffusion, which is P-type and in proximity to said first surface of said monolithic body;
- a second patterned diffusion, which is P-type, and in proximity to said first surface, and extends deeper into said monolithic body than said first diffusion does;
- a third patterned diffusion, which is heavily doped, and N-type, and extends from said substrate toward said first surface of said monolithic body;
- wherein each said vertical-current-flow MOS transistor comprises
- a respective portion of said first diffusion, which is laterally shaped to define a body portion of said transistor;
- and
- a source terminal surrounded by said body portion;
- and
- an n-type drift region to which said body portion forms a p/n junction;
- and
- an insulated gate which is capacitively coupled to at least a portion of said body portion;
- and
- a respective portion of said third diffusion, which is laterally shaped to provide a drain portion of said transistor, said drain portion being separated from said body portion by said n-type drift region;
- and wherein at least one said vertical-current-flow MOS transistor further comprises a respective portion of said second diffusion adjoining said body portion thereof;
- and wherein the minimum separation between said second and third diffusions, in any one said MOS transistor, is greater than the minimum separation between said first and third diffusions.
15 more elements
An integrated circuit device comprising:
- at least one monolithic body of semiconductor material, including a heavily doped N-type substrate and one or more epitaxial layers thereon, an outermost one of said epitaxial layers being N-type and extending to a first surface of said monolithic body;
- a power stage and an integrated control circuit, said power stage containing one or more vertical-current-flow MOS transistors;
- said power stage including at least:
- a first patterned diffusion, which is P-type and in proximity to a first surface of said monolithic body;
- a second patterned diffusion, which is P-type, and in proximity to said first surface, and extends deeper into said monolithic body than said first diffusion does, and forms a junction to said epitaxial layer which has less curvature than the junction formed by said first diffusion with said epitaxial layer;
- a third patterned diffusion, which is heavily doped, and N-type, and extends from said substrate toward said first surface of said monolithic body;
- an additional patterned diffusion, which is heavily doped and N-type, and is in proximity to said first surface of said monolithic body, and is shallower than said first diffusion;
- wherein each said vertical-current-flow MOS transistor comprises
- a respective portion of said first diffusion, which is laterally shaped to define a body portion of said transistor;
- and
- a source terminal, comprising a respective portion of said additional diffusion which is surrounded by said body portion;
- and
- an n-type drift region, comprising a portion of said epitaxial layer, to which said body portion forms a p/n junction;
- and
- an insulated gate which is capacitively coupled to at least a channel portion of said body portion;
- and
- a respective portion of said third diffusion, which is laterally shaped to provide a drain portion of said transistor, said drain portion being separated from said body portion by said n-type drift region;
- and wherein at least one said vertical-current-flow MOS transistor further comprises a respective portion of said second diffusion adjoining said body portion thereof, such that the minimum separation between said second and third diffusions is greater than the minimum separation between said first and third diffusions.
15 more elements
An integrated circuit device comprising:
- at least one monolithic body of semiconductor material, including a heavily doped N-type substrate and one or more epitaxial layers thereon, an outermost one of said epitaxial layers being N-type and extending to a first surface of said monolithic body;
- a power stage and an integrated control circuit, said power stage containing one or more vertical-current-flow MOS transistors, and said control circuit containing one or more npn bipolar transistors;
- said power stage including at least;
- a first patterned diffusion, which is P-type and in proximity to a first surface of said monolithic body;
- a second patterned diffusion, which is P-type, and in proximity to said first surface, and extends deeper into said monolithic body than said first diffusion does;
- and
- a third patterned diffusion, which is heavily doped, and N-type, and extends from said substrate toward said first surface of said monolithic body;
- wherein each said vertical-current-flow MOS transistor comprises
- a respective portion of said first diffusion, which is laterally shaped to define a body portion of said transistor;
- and
- a source terminal surrounded by said body portion;
- and
- an n-type drift region to which said body portion forms a p/n junction;
- and
- an insulated gate which is capacitively coupled to at least a portion of said body portion;
- and
- a respective portion of said third diffusion, which is laterally shaped to provide a drain portion of said transistor, said drain portion being separated from said body portion by said n-type drift region;
- and wherein at least one said vertical-current-flow MOS transistor further comprises a respective portion of said second diffusion adjoining said body portion thereof;
- and wherein multiple ones of said npn bipolar transistors each comprise an N-type emitter region overlying a p-type base region overlying an n-type collector region;
- and wherein said first patterned diffusion also provides a base region for bipolar transistors in said control circuit;
- and wherein said second patterned diffusion also provides said p-type lateral isolation regions;
- and wherein said source terminal of said vertical-current-flow MOS transistor is provided by a patterned shallow n+ diffusion which also provides N-type emitter regions of one or more npn bipolar transistors of said control circuit;
- and wherein the minimum separation between said second and third diffusions is greater than the minimum separation between said first and third diffusions.
20 more elements
Dependencies are inferred from the claim text.