Semiconductor device and method of manufacturing the same

A memory cell comprising:

• a semiconductor layer including a top surface;
• a first depression formed in said semiconductor layer such that said first depression is disposed within said semiconductor layer below said top surface;
• a second depression formed within said semiconductor layer and linked to said first depression, said second depression formed deeper within said semiconductor layer than said first depression;
• a first doped region formed adjacent said second depression;
• an insulating layer formed within said first and second depressions;
• a conductor formed adjacent said insulating region within said first and second depressions;
• an insulating film formed on top of said conductor at an interface wherein said interface is formed inside said first depression below said top surface;
• a second doped region formed in said semiconductor layer and spaced from said first doped region by a channel region;
• and
• a gate disposed over said channel region.

A semiconductor device comprising:

• a semiconductor layer including a top surface;
• a first depression formed in said semiconductor layer and extending below said top surface;
• a second depression formed in said semiconductor layer and linked to said first depression, said second depression formed deeper than said first depression;
• a first conductor formed with said second depression thereby creating a third depression within said second depression;
• a second conductor formed within said first and third depressions, said second conductor insulated from said first conductor;
• and
• an insulating film formed on top of said second conductor at an interface wherein the interface between the insulating film and the second conductor is formed inside the first depression.