Non-volatile semiconductor memory using a thin film transistor
AssigneeKabushiki Kaisha Toshiba
InventorKiyofumi Ochii
Life of this patent
Estimating the term…
Loading patent…
AssigneeKabushiki Kaisha Toshiba
InventorKiyofumi Ochii
Estimating the term…
A MOS transistor has a floating gate, which forms a memory cell of EPROM, and a control gate. The control gate is formed of a thin film. An impurity concentration of a region corresponding to the floating gate is lower than that of the other regions. The region having low impurity concentration functions as a channel region of a thin film transistor. The floating gate functions as a gate of the thin film transistor. In the memory cell in which an electron is written in the floating gate, a threshold voltage of the thin film transistor rises, and the thin film transistor is set to be in an off state. In the memory cell in which no electron is written in the floating gate, the threshold voltage of the thin film transistor lowers, and the thin film transistor is set to be in an on state. If the voltage of said control gate rises in a reading operation, an inversion layer is formed in the only cell of the erasing state and the high voltage of the control gate is supplied to a channel region, and the MOS transistor is turned on. Due to this, the voltage, which is higher than the threshold value of the memory cell of the writing state, can be supplied to the control gate.
A semiconductor memory device, comprising:
A semiconductor device, comprising:
A semiconductor memory device comprising:
Dependencies are inferred from the claim text.