Bit line arrangement for integrated circuits

A bit line arrangement for integrated circuits, comprising:

• a plurality of bit lines and a plurality of cells;
• each bit line of the plurality of bit lines having a row of contacts in a first direction, each contact thereof contacting a conductive region of a respective cell and being widened to form a contact surface only in an area of said contacts;
• contacts of adjacent bit lines being offset relative to one another thereby forming at least a 3-fold stagger;
• a distance between bit line edges of two adjacent bit lines having everywhere a substantially constant value within a range of manufacturing tolerances;
• given a prescribed geometrical arrangement and size of the contacts, bit line edges of a given bit line of the plurality of bit lines represent, in segments, straight lines which have two gradients which differ at least in sign and differ from 0 with respect to the first direction, the straight lines being three straight lines g.sub.1, g.sub.2, g.sub.3 that satisfy the following rule of construction:
• g.sub.1 :
• mid-point 0 of a connecting section between contact K.sup.i and a contact, adjacent in the negative x-direction, of the i.sup.th bit line;
• the mid-point having coordinates, -2 R.sub.St ;
• 0;
• mid-point Q of a connecting section between contact K.sup.i-1 and a contact, adjacent in the positive x-direction, of an adjacent i-1 bit line;
• mid-point Q having coordinates -R.sub.St, R.sub.BL ;
• circle K.sub.Q around mid-point Q of radius r.sub.Q =b.sub.B +b.sub.Sp ;
• tangent to the circle k.sub.Q through mid-point 0;
• this tangent being a path axis of a bit line section being sought;
• g.sub.1 being parallel to the path axis at a distance 1/2 b.sub.S ;
• g.sub.2 :
• connecting section z between L.sub.a.sup.i and L.sub.c.sup.i-1 with mid-point Z;
• g.sub.2 being perpendicular to connecting section z at a distance 1/2 b.sub.SP from mid-point Z;
• g.sub.3 :
• g.sub.3 being produced by translation of g.sub.1 in the positive x-direction by 4R.sub.St ;
• where:
• b.sub.B :
• is the width of a bit line outside a contact surface;
• b.sub.Sp :
• is the distance between edges of adjacent bit lines;
• R.sub.BL :
• is a bit line raster in the y-direction;
• R.sub.St :
• is a stagger raster which is equal to the offset of the contacts of adjacent bit lines in the x-direction;
• n:
• is a whole number for an n-fold stagger of n+1 bit lines;
• K.sup.i :
• denotes the i=1 . . . n+1 contacts of the n+1 bit lines;
• and
• L.sub.a.sup.i -L.sub.d.sup.i :
• denotes corner points of the contacts K.sup.i, i=1, . . n+1.

A bit line arrangement for integrated circuits, comprising:

• a plurality of bit lines and a plurality of cells;
• each bit line of the plurality of bit lines having a row of contacts in a first direction, each contact thereof contacting a conductive region of a respective cell and being widened to form a contact surface only in an area of said contacts;
• contacts of adjacent bit lines being offset relative to one another thereby forming at least a 3-fold stagger;
• a distance between bit line edges of two adjacent bit lines having everywhere a substantially constant value within a range of manufacturing tolerances;
• and
• given a prescribed geometrical arrangement and size of the contacts, the bit line edges represent, in segments, straight lines which have at least three different gradients.