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US 5,315,150 AGranted
Semiconductor device and method of manufacturing the same
AssigneeSeiko Epson Corporation
InventorTomoyuki Furuhata
Life of this patent
Estimating the term…
Abstract
A semiconductor device including a MOS element having a buried contact structure. The buried contact structure includes a first contact diffused region formed by diffusion from a polycrystalline silicon layer and a second contact diffused region formed by diffusion deeper than the first contact diffused region, so that a parasitic resistance of the MOS element can be reduced. In a composite element composed of the MOS element and a bipolar element, partly since the first contact diffused region and an emitter diffused region of the bipolar element can be formed simultaneously, and partly since the depth of connection of the emitter diffused region, with the parasitic resistance of the MOS element being reduced, it is possible to realize a high-speed operation.
Claims20
A semiconductor device comprising:
- (a) a semiconductor substrate;
- (b) an MOS element formed on a main surface of said semiconductor substrate, and having a buried contact structure;
- and
- (c) said buried contact structure including a first contact diffused region formed in said main surface of said semiconductor substrate by diffusion from a polycrystalline silicon layer, and a second contact diffused region formed by diffusion, said second contact diffused region being located deeper in said semiconductor substrate than said first contact diffused region such that said first contact diffused region overlays at least a portion of said second contact diffused region;
- wherein said first contact diffused region has a depth of diffusion of 0.1 to 0.3 .mu.m and said second contact diffused region has a depth of diffusion of 0.5 to 0.8 .mu.m, and
- wherein said MOS element comprises a source/drain diffused region, said depth of diffusion of said second contact diffused region being larger than a depth of said source/drain diffused region of said MOS element.
3 more elements
A method of manufacturing a semiconductor device, comprising the steps of:
- (a) forming a lower contact diffused region in a silicon substrate by forming a field oxide film and a gate oxide film on said silicon substrate and doping said silicon substrate with an impurity of a large diffusion constant to form a buried contact structure forming region in said silicon substrate;
- (b) forming an upper contact diffused region in said silicon substrate over said lower contact diffused region by forming openings in the gate oxide film, forming a polycrystalline silicon layer on the silicon substrate over said lower contact diffused region and doping said silicon substrate with an impurity of a small diffusion constant into the buried contact structure forming region via the openings such that said upper contact diffused region overlays at least a portion of said lower contact diffused region;
- (c) etching the polycrystalline silicon layer thereby forming a gate electrode and a source/drain electrode;
- and
- (d) doping said silicon substrate with an impurity between said gate electrode and said source/drain electrode thereby forming a source/drain diffused region in said silicon substrate.
2 more elements
A semiconductor device comprising:
- (a) a semiconductor substrate;
- (b) a bipolar element formed on a main surface of said semiconductor substrate;
- (c) an MOS element formed on the main surface of said semiconductor substrate and having a buried contact structure;
- (d) an emitter electrode of said bipolar element and a source/drain electrode of said MOS element being in the form of a single polycrystalline silicon layer;
- (e) said buried contact structure of said MOS element including a first contact diffused region formed in said main surface of said semiconductor substrate by impurity diffusion of a first material from said polycrystalline silicon layer and a second contact diffused region formed by previous impurity diffusion of a second material, said second contact diffused region being located deeper in said semiconductor substrate than said first contact diffused region such that said first contact diffused region overlays at least a portion of said second contact diffused region;
- and
- (f) an emitter diffused region of said bipolar element and said first contact diffused region being formed in said main surface of said semiconductor substrate by impurity diffusion from said polycrystalline silicon layer;
- wherein said first contact diffused region has a depth of diffusion of 0.1 to 0.3 .mu.m and said second contact diffused region has a depth of diffusion of 0.5 to 0.8 .mu.m, and
- wherein said MOS element comprises a source/drain diffused region, said depth of diffusion of said second contact diffused region being larger than a depth of said source/drain diffused region of said MOS element.
6 more elements
A method of manufacturing a semiconductor device having a MOS element and a bipolar element on a silicon substrate, the method comprising the steps of:
- (a) forming a well on said silicon substrate;
- (b) forming a field oxide film and a gate oxide film on said well;
- (c) forming a lower contact diffused region of said MOS element and a collector diffused region of said bipolar element in said well by doping said well with an impurity of a large diffusion constant, said lower contact diffused region being part of a buried contact structure forming region of said MOS element;
- (d) forming an upper contact diffused region of said MOS element over said lower contact diffused region and an emitter diffused region of said bipolar element spaced from said collector diffused region by masking said MOS element, doping said well with an impurity thereby forming a base diffused region of said bipolar element, forming openings in said gate oxide film over said buried contact structure forming region and said base diffused region, forming a polycrystalline silicon layer on said silicon substrate over said lower contact diffused region and said base diffused region, and doping said well with an impurity of a small diffusion constant through said openings in said gate oxide film to form said upper contact diffused region over said lower contact diffused region and said emitter diffused region in said base diffused region such that said upper contact diffused region overlays at least a portion of said lower contact diffused region;
- (e) forming a gate electrode and a source/drain electrode of said MOS element and an emitter electrode of said bipolar element by etching said polycrystalline layer;
- and
- (f) forming a source/drain diffused region in said well by masking said bipolar element and doping said well with an impurity between said gate electrode and said source/drain electrode.
4 more elements
A semiconductor device comprising:
- (a) a semiconductor substrate;
- (b) an MOS element formed on a main surface of said semiconductor substrate and having a buried contact structure;
- and
- (c) said buried contact structure including a first contact diffused region formed in said main surface of said semiconductor substrate by diffusion from a polycrystalline silicon layer, and a second contact diffused region formed by diffusion, said second contact diffused region being located deeper in said semiconductor substrate than said first contact diffused region such that said first contact diffused region overlays at least a portion of said second contact diffused region;
- wherein said first contact diffused region has a depth of diffusion of 0.1 to 0.3 .mu.m and said second contact diffused region has a depth of diffusion of 0.5 to 0.8 .mu.m, and
- wherein said MOS element comprises a source/drain diffused region, an impurity concentration in said first contact diffused region being no less than an impurity concentration in said source/drain diffused region of said MOS element.
3 more elements
A semiconductor device comprising:
- (a) a semiconductor substrate;
- (b) a bipolar element formed on a main surface of said semiconductor substrate;
- (c) an MOS element formed on the main surface of said semiconductor substrate and having a buried contact structure;
- (d) an emitter electrode of said bipolar element and a source/drain electrode of said MOS element being in the form of a single polycrystalline silicon layer;
- (e) said buried contact structure of said MOS element including a first contact diffused region formed in said main surface of said semiconductor substrate by impurity diffusion of a first material from said polycrystalline silicon layer and a second contact diffused region formed by previous impurity diffusion of a second material, said second contact diffused region being located deeper in said semiconductor substrate than said first contact diffused region such that said first contact diffused region overlays at least a portion of said second contact diffused region;
- and
- (f) an emitter diffused region of said bipolar element and said first contact diffused region being formed in said main surface of said semiconductor substrate by impurity diffusion from said polycrystalline silicon layer;
- wherein said first contact diffused region has a depth of diffusion of 0.1 to 0.3 .mu.m and said second contact diffused region has a depth of diffusion of 0.5 to 0.8 .mu.m, and
- wherein said MOS element comprises a source/drain diffused region, an impurity concentration in said first contact defused region being no less than an impurity concentration in said source/drain diffused region of said MOS element.
6 more elements
Dependencies are inferred from the claim text.