Semiconductor memory device having specific layout configuration of n-MOS memory cells

A semiconductor memory device including a plurality of memory cells arranged in a matrix on a chip, each memory cell including a flip-flop having a first set of one driver transistor and one load element, and a second set of one driver transistor and one load element, said first and second sets being cross-coupled, and a pair of transfer gate transistors connected between a pair of data retaining nodes of the flip-flop and a pair of complementary bit lines, respectively, and responsive to a potential at a corresponding word line, the semiconductor memory device comprising:

• a gate region of each driver transistor arranged obliquely with respect to a first direction of the chip;
• a source/drain region of each drive transistor arranged obliquely with respect to the first direction of the chip;
• first contact windows arranged in a line substantially parallel with the first direction and connecting each source/drain region of the driver transistors to a power supply line provided in the first direction;
• and
• second contact windows arranged every one contact window in a zigzag manner with respect to the first direction and connecting each source/drain region of the transfer gate transistors to the corresponding bit line.