Integrated circuit polishing method

A method of fabrication of an integrated circuit, said method comprising the steps of:

• providing a semiconductor wafer having a surface layer of a first material to be planarized in a chemical mechanical polishing process, said first material having a first polish rate in the chemical mechanical polishing process;
• masking the surface layer to expose only a portion of the surface layer;
• altering said exposed portion of said surface layer of said first material to create a second material which has a second removal rate in the chemical mechanical polishing process different than said first material;
• and
• polishing said surface layer in the chemical mechanical polishing process.

A method of fabrication of an integrated circuit, said method comprising the steps of:

• providing a semiconductor wafer having a surface layer of a first material to be planarized in a chemical mechanical polishing process;
• altering a portion of said surface layer of material to create a second material which responds differently to the chemical mechanical polishing process than said first material wherein said step of altering comprises doping selected portions of said first material;
• and
• polishing said surface layer in a chemical mechanical polishing process.

A method of fabrication of an integrated circuit, said method comprising the steps of:

• providing a semiconductor wafer having a surface layer of a first material to be planarized in a chemical mechanical polishing process, said first material having a first polish rate in the chemical mechanical polishing process;
• altering a portion of said surface layer of said first material to create a second material which has a second removal rate in the chemical mechanical polishing process different than said first material wherein said step of altering comprises the steps of:
• (i) masking said layer of material;
• (ii) exposing said masked area of material to a modification process to modify selected areas of said layer of material;
• and
• (iii) polishing said surface layer in the chemical mechanical polishing process.

A method of fabrication of an integrated circuit, said method comprising the steps of:

• providing a semiconductor wafer having a surface layer of a first material to be planarized in a chemical mechanical polishing process;
• masking the surface layer to expose only a portion of the surface layer;
• altering said exposed portion of said surface layer of material above a wafer trough to create a region of a second material more resistant to the chemical mechanical polishing process than said first material;
• and
• polishing said surface layer in the chemical mechanical polishing process until all of said second material is removed and said first material is planarized.

A method of fabrication of an integrated circuit, said method comprising the steps of:

• providing a semiconductor wafer having a surface layer of a first material to be planarized in a chemical mechanical polishing process, the surface layer having an upper surface;
• altering a portion of said surface layer of material at either side of a trough to create a region of a second material less resistant to the chemical mechanical polishing process than said first material while leaving a portion of said surface layer over said trough unaltered, wherein the upper surface includes a region of said unaltered first material and said region of said second material;
• and
• polishing said surface layer in the chemical mechanical polishing process until all of said region of second material is removed and said first material is planarized.