Semiconductor memory device
AssigneeSharp Kabushiki Kaisha
InventorMasahiko Yanagi
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device including a substrate on which a memory cell array portion and a peripheral circuit portion for the memory cell array portion are provided, the surface of the memory cell array portion being higher than the surface of the peripheral circuit portion. A glass layer is formed on the peripheral circuit portion with the glass layer having a predetermined thickness for offsetting the difference in height between the surface of the memory cell array portion and that of the peripheral circuit portion, so as to provide a substantially even surface over the memory cell array portion and the peripheral circuit portion. A metal wiring for the memory cell array portion and the peripheral circuit portion is formed in a predetermined pattern on the substantially even surface.
Claims4
A method of forming a semiconductor memory device having a substantially even surface, said method comprising:
- forming a memory cell array portion and a peripheral circuit portion on a semiconductor substrate wherein the height of the surface of said memory cell array portion above the substrate exceeds that of said peripheral circuit portion;
- forming a first insulating film of a material having a first etching rate on the surfaces of said memory cell array portion and said peripheral circuit portion;
- forming a glass layer on the entire surface of said first insulating layer, said glass layer having a second etching rate and having a predetermined thickness sufficient to offset the difference in surface heights of said memory cell array and peripheral circuit portions;
- isotropically etching said glass layer to remove that portion of said glass layer formed on the said memory cell array portion so that the surface heights of said glass layer and said first insulating layer formed on said memory cell array portion are substantially flush with each other;
- and
- forming a metal wiring for said memory cell array portion and said peripheral circuit portion on said substantially flush surfaces.
Dependencies are inferred from the claim text.