Semiconductor device
AssigneeNEC Corporation
InventorToshikatsu Jinbo
Life of this patent
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Abstract
A semiconductor device includes a P-type semiconductor substrate, an N-type well region formed on the surface of the substrate, a P-type well region formed in the N-type well region and a MOSFET as a flash memory element formed in the P-type well region. Upon erasure of the information in the flash memory, a high voltage is temporarily charged to the P-type and N-type well regions, in such a manner that a first high voltage pulse of a predetermined width is charged to the N-type well region, a second high voltage pulse having a pulse width narrower than the pulse width of the first pulse is charged to the P-type well region in a period between the initiation end and the termination end of the first pulse.
Claims16
A semiconductor device comprising:
- a one conductivity type semiconductor substrate;
- an opposite conductivity type well region formed on the surface of said semiconductor substrate;
- a one conductivity type well region formed on said opposite conductivity type well region;
- an insulated gate type field effect transistor formed in said one conductivity type well region;
- and
- well voltage control means for applying a first pulse, having a voltage level sufficient for establishing a reverse bias at the PN junction between said opposite conductivity type well region and said one conductivity type well region, to a first portion of said opposite conductivity type well region for a given period, and applying a second pulse, having said voltage level, to a second portion of said one conductivity type well region in a period between the initiation timing and termination timing of said first pulse, which second pulse has an initiation timing later than the initiation timing of said first pulse and a termination timing earlier than the termination timing of said first pulse.
A semiconductor device comprising a semiconductor substrate of one conductivity type, a first well region of an opposite conductivity type formed in said semiconductor substrate, a second well region of said one conductivity type formed in said first well region, at least one insulated gate field effect transistor formed in said second well region, a first contact region of said opposite conductivity type formed in a part of said first well region, a second contact region of said one conductivity type formed in a part of said second well region, and a well voltage control circuit supplying first and second well voltages respectively to said first and second contact regions and changing each of said first and second well voltages between a first voltage level and a second voltage level in response to a change in logic level of a control signal such that said first well voltage is changed from said first voltage level to said second voltage level at a first timing and said second well voltage is changed from said first voltage level to said second voltage level at a second timing after said first timing in response to a change of said control signal from a first logic level to a second logic level and that said first well voltage is changed from said second voltage level to said first voltage level at a third timing and said second well voltage level at a third timing and said second well voltage is changed from said second voltage level to said first voltage level at a fourth timing before said third timing in response to a change of said control signal from said second logic level to said first logic level.
A semiconductor device comprising:
- a one conductivity type semiconductor substrate;
- an opposite conductivity type well region formed on the surface of said semiconductor substrate;
- a one conductivity type well region formed on said opposite conductivity type well region;
- an insulated gate type field effect transistor formed in said one conductivity type well region;
- and
- well voltage control means for applying a first pulse having a predetermined voltage level to a portion of said opposite conductivity type well region for a first period of time defined by a first initiation timing and a first termination timing and for applying a second pulse having a said predetermined voltage level to a portion of said one conductivity type well region for a second period of time defined by a second initiation timing and a second termination timing, said second initiation timing occurring later than said first initiation timing and said second termination timing occurring earlier than said first termination timing.
Dependencies are inferred from the claim text.