SOI type vertical channel field effect transistor and process of manufacturing the same

A process for manufacturing a vertical channel field of effect transistor comprising the steps of:

• forming a drain layer on at least a portion of a front surface of a first semiconductor substrate;
• forming a first insulating film on the drain layer;
• etching the front surface of the first semiconductor substrate to form a first groove using the first insulating film as a mask;
• forming a second insulating film over the surface of the first semiconductor substrate and the first insulating film;
• etching the second insulating film to form a first side wall on a side surface of the groove;
• etching the first semiconductor substrate using the first side wall as a mask;
• forming a third insulating film on the front surface of the first semiconductor substrate;
• forming a polycrystal silicon layer on the third insulating film;
• cladding the polycrystal silicon layer to a second semiconductor substrate;
• polishing a rear surface of the first semiconductor substrate to expose the third insulating film;
• doping the exposed surface of the first semiconductor substrate to form a source region;
• forming a second side wall above the source region;
• selectively etching the first semiconductor substrate using the second side wall as mask to form a vertical channel;
• forming a gate insulating film on said vertical channel;
• forming a gate electrode in the vertical channel;
• selectively etching the second side wall to from an opening;
• and
• forming a drain electrode in the opening on said drain region.