Semiconductor memory device and manufacturing method thereof

A semiconductor memory device comprising:

• a diffusive region for a source formed in the shape of a band on a substrate to construct a source region of plural memory cells;
• a diffusive region for a drain formed in the shape of a band in parallel with said diffusive region for a source and alternated with this diffusive region for a source to construct a drain region of the plural memory cells;
• a first word line layer electrically insulated from said diffusive regions for a source and a drain and formed such that the first word line layer crosses the diffusive regions for a source and a drain;
• and
• a second word line layer electrically insulated from said diffusive regions for a source and a drain and said first word line layer and formed in parallel with the first word line layer;
• the second word line layer including:
• a flat portion arranged between two first word line layers adjacent onto both sides of said second word line layer;
• a first side wall portion arranged on a side of one of said two adjacent first word line layers on both sides of said second word line layer and connected to one end of said flat portion and having a thickness substantially increased;
• a second side wall portion arranged on a side of the other of said two adjacent first word line layers on both sides of said second word line layer and connected to another end of said flat portion and having a thickness substantially increased;
• a first overlapping portion connected to said first side wall portion and extending onto an edge portion of one of said two first word line layers such that the first overlapping portion overlaps this edge portion;
• and
• a second overlapping portion connected to said second side wall portion and extending onto an edge portion of the other of said two first word line layers such that the second overlapping portion overlaps this edge portion;
• the semiconductor memory device further comprising a channel region including:
• an a-region on a substrate surface located on a lower side of said flat portion within a region prescribed between said diffusive regions for a source and a drain;
• and
• two b-regions on the substrate surface arranged on both sides of the a-region and located on lower sides of said first and second side wall portions;
• the channel region being formed to provide four states of electric current values with respect to each of the memory cells;
• and
• the four states being composed of:
• a first state in which there is no core implantation in each of said a-region and said two b-regions;
• a second state in which there is core implantation only in said a-region;
• a third state in which there is core implantation only in said two b-regions;
• and
• a fourth state in which there is core implantation in all of said a-region and said two b-regions.