Semiconductor vertical MOSFET inverter circuit

A semiconductor device comprising:

• a semiconductor substrate (1);
• at least one first column-shaped semiconductor layer (10) of a first channel type formed on said semiconductor substrate (1) in order of first, second and third regions, and having a side surface;
• at least one second column-shaped semiconductor layer (11) of a second channel type selectively laminated on said first column-shaped semiconductor layer (10) in order of first, second and third regions and having a side surface;
• a gate insulation film (8) formed on the side surfaces of said first column-shaped semiconductor layer (10) and said second column-shaped semiconductor layer (11);
• a gate electrode (9) surrounding said first and second column-shaped semiconductor layer (10) and (11) and formed on said insulation film (8) to extend to an external portion of said first column-shaped semiconductor layer (10);
• a first source layer (2) and a first drain layer (4) respectively formed in the first and third region of said first column-shaped semiconductor layer (10);
• a second drain layer (5) and a second source layer (7) respectively formed in the first and third region of said second column-shaped semiconductor layer (11);
• an input terminal (15) connected to said gate electrode (9) lead out to the exterior of said first column-shaped semiconductor layer (10);
• an output terminal (15) connected to said second drain layer (5) formed on and in low-resistance contact with said first drain layer (4);
• a first power source terminal (16) connected to said first source layer (2) of said first column-shaped semiconductor layer (10);
• and
• a second power source terminal (17) connected to said second source layer (7);
• wherein said first source layer (2), first drain layer (4) and gate electrode (9) constitute a first MOS transistor and said second source layer (7), second drain layer (5) and gate electrode (9) constitute a second MOS transistor, and said first column-shaped semiconductor layer (10) is constructed by at least two column-shaped semiconductor layers and at least open of said second column-shaped semiconductor layers (11) is selectively formed on said first column-shaped semiconductor layer (10).

A semiconductor device comprising:

• a semiconductor substrate (1);
• at least one first column-shaped semiconductor layer (10) of a first channel type formed on said semiconductor substrate (1) in order of first, second and third regions, and having a side surface;
• at least one second column-shaped semiconductor layer (11) of a second channel type selectively laminated on said first column-shaped semiconductor layer (10) in order of first, second and third regions, and having a side surface;
• a gate insulation film (8) formed on the side surfaces of said first column-shaped semiconductor layer (10) and said second column-shaped semiconductor layer (11);
• a gate electrode (9) completely surrounding said first and second column-shaped semiconductor layer (10) and (11), and formed on said insulation film (8) to extend to an external portion of said first column-shaped semiconductor layer (10);
• a first source layer (2) and a first drain layer (4) respectively formed in the first and third region of said first column-shaped semiconductor layer (10);
• and
• a second drain layer (5) and a second source layer (7), respectively formed in the first and third region of said second column-shaped semiconductor layer (11);
• wherein said first source layer (2), first drain layer (4) and gate electrode (9) constitute a first MOS transistor and said second source layer (7), second drain layer (5) and gate electrode (9) constitute a second MOS transistor.

A semiconductor device comprising:

• a semiconductor substrate (1);
• at least one first column-shaped semiconductor layer (10) of a first channel type formed on said semiconductor substrate (1) in order of first, second and third regions, and having a side surface;
• at least one second column-shaped semiconductor layer (11) of a second channel type selectively laminated on said first column-shaped semiconductor layer (10) in order of first, second and third regions, and having a side surface;
• a gate insulation film (8) formed on the side surfaces of said first column-shaped semiconductor layer (10) and said second column-shaped semiconductor layer (11);
• a gate electrode (9) surrounding said first and second column-shaped semiconductor layer (10) and (11), and formed on said insulation film (8) to extend to an external portion of said first column-shaped semiconductor layer (10);
• a first source layer (2) and a first drain layer (4) respectively formed in the first and third region of said first column-shaped semiconductor layer (10);
• and
• a second drain layer (5) and a second source layer (7) respectively formed in the first and third region of said second column-shaved semiconductor layer (11);
• wherein said first source layer (2), first drain layer (4) and gate electrode (9) constitute a first MOS transistor and said second source layer (7), second drain layer (5) and gate electrode (9) constitute a second MOS transistor, and said first column-shaped semiconductor layer (10) is constructed by at least two column-shaped semiconductor layers and at least one of said second column-shaped semiconductor layers (11) is selectively formed on said first column-shaped semiconductor layer (10).

A semiconductor device comprising:

• a semiconductor substrate (1);
• at least one first column-shaped semiconductor layer (10) of a first channel type formed on said semiconductor substrate (1) in order of first, second and third regions, and having a side surface;
• at least one second column-shaped semiconductor layer (11) having the same channel type as that of said first column-shaped semiconductor layer (10), selectively laminated on said first column-shaped semiconductor layer (10) in order of first, second and third regions, and having a side surface;
• a gate insulation film (8) formed on the side surfaces of said first column-shaped semiconductor layer (10) and said second column-shaped semiconductor layer (11);
• a gate electrode (9) completely surrounding said first and second column-shaped semiconductor layer (10) and (11), and formed on said insulation film (8) to extend to an external portion of said first column-shaped semiconductor layer (10);
• a first source layer (2) and a first drain layer (4) respectively formed in the first and third region of said first column-shaped semiconductor layer (10);
• and
• a second drain layer (5) and a second source layer (7) respectively formed in the first and third region of said second column-shaped semiconductor layer (11);
• wherein said first source layer (2), first drain layer (4) and gate electrode (9) constitute a first MOS transistor and said second source layer (7), second drain layer (5) and gate electrode (9) constitute a second MOS transistor.

A semiconductor device comprising:

• a semiconductor substrate (1);
• at least one first column-shaped semiconductor layer (10) of a first channel type formed on said semiconductor substrate (1) in order of first, second and third regions, and having a side surface;
• at least one second column-shaped semiconductor layer (11) having the same channel type as that of said first column-shaped semiconductor layer (10), selectively laminated on said first column-shaped semiconductor layer (10) in order of first, second and third regions, and having a side surface;
• a gate insulation film (8) formed on the side surfaces of said first column-shaped semiconductor layer (10) and said second column-shaped semiconductor layer (11);
• a gate electrode (9) surrounding said first and second column-shaped semiconductor layer (10) and (11), and formed on said insulation film (8) to extend to an external portion of said first column-shaped semiconductor layer (10);
• a first source layer (2) and a first drain layer (4) respectively formed in the first and third region of said first column-shaped semiconductor layer (10);
• and
• a second drain layer (5) and a second source layer (7) respectively formed in the first and third region of said second column-shaped semiconductor layer (11);
• wherein said first source layer (2),first drain layer (4) and gate electrode (9) constitute a first MOS transistor and said second source layer (7), second drain layer (5) and gate electrode (9) constitute a second MOS transistor, and said first column-shaped semiconductor layer (10) is constructed by at least two column-shaped semiconductor layers and at least one of said second column-shaped semiconductor layers (11) is selectively formed on said first column-shaped semiconductor layer (10).