Interconnect structure in semiconductor device and method for making the same

A method of fabricating an interconnect structure in a semiconductor device comprising the steps of:

• forming, on an active layer of GaAs, a source/drain electrode of AuGe/Ni/Au and a gate electrode of WSi;
• forming, in a contact hole region on the gate electrode of WSi, a film of Ti/Pt/Au by a vacuum evaporation method;
• forming a film of SiO.sub.2 as a protective film over a substrate and also a film of WSiN over the substrate by a sputtering method;
• forming on said film of SiO.sub.2 a resistor element of WSiN by a patterning using a photoresist and a dry-etching using an SF.sub.6 gas;
• forming, only in the contact hole region of the resistor element of WSiN, a film of Ti/Au by the vacuum evaporation method;
• depositing again, on the resulting surface, a film of SiO.sub.2 followed by a photoresist coating and etch-back process, with SiO.sub.2 being deposited and flattened thereby forming a flattened layer;
• forming, in said flattened layer, a contact hole on each of the source/drain electrode and the gate electrode and a contact hole on the resistor element of WSiN all at the same time by the dry-etching using a CF.sub.4 gas;
• forming, as an interconnect, a layer of Ti/Pt/Au over the entire surface of the substrate by the sputtering and vapor deposition method, and patterning an interconnect region by using a photoresist;
• gold-plating to said layer of Ti/Pt/Au with this layer being used as one electrode of plating;
• and
• removing the photoresist and removing the layer of Ti/Pt/Au in areas other than the interconnect region by milling for an Au plated interconnect.