Voltage reducing circuit
AssigneesFujitsu Limited, Fujitsu VLSI Limited
InventorsTomio Nakano, Yoshiharu Kato, Hidenori Nomura
Life of this patent
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Abstract
In a semiconductor integrated circuit for taking in an external power source voltage from outside the semiconductor chip, the external power source voltage is dropped by a voltage dropping unit installed inside the semiconductor chip and the external power source voltage in the semiconductor integrated circuit, as dropped is supplied as an internal power source voltage to the semiconductor chip and used as the internal power source voltage, a plurality of voltage dropping units are installed for each of a plurality of semiconductor circuit block installed inside the semiconductor chip, and the voltage fluctuation of an internal power source is effectively suppressed in the event that a circuit consuming a very high current is operated.
Claims8
A semiconductor integrated circuit for receiving an external power source voltage from outside of a semiconductor chip, comprising:
- an external power source terminal (VccPAD) for supplying said external power source voltage as an internal power source voltage into said semiconductor chip;
- a voltage dropping means (A) within said semiconductor chip for dropping said external power source voltage, wherein said voltage dropping means comprises a plurality of voltage dropping means (A1 through An) for connecting said external power source terminal (VccPAD) within said semiconductor chip and for changing said external power source voltage to a desired internal power source voltage;
- and
- a plurality of semiconductor circuit blocks (C11 through C1n) within said semiconductor chip respectively coupled to said voltage dropping means (A1 through An),
- wherein the voltage dropping means (A1 through An) for each of said semiconductor circuit blocks (C11 through C1n) includes at least 1 MOS transistor (A11 through A1n), and
- wherein drains of said respective MOS transistors (A11 through A1n) are connected in common through a first common line for connection to said external power source terminal (VccPAD), and gates of respective MOS transistors (A11 through A1n) are also connected to said first common line.
Dependencies are inferred from the claim text.