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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKaoru Motonami, Katumi Suizu
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A contact structure for interconnection in semiconductor devices provides electrical contact between an impurity-diffused region formed in a silicon substrate and a polycrystalline silicon layer through a contact hole. The contact structure for interconnection comprises the silicon substrate, the impurity-diffused region, an insulating oxide film, the interconnection layer formed of a polycrystalline silicon layer containing impurities. The impurity-diffused region is formed in a main surface of the silicon substrate as a source/drain region of an MOS transistor. The insulating oxide film has a contact hole formed therethrough to reach a surface of this impurity-diffused region. A sidewall layer of polycrystalline silicon is formed on the bottom peripheral edge of the contact hole. The interconnection layer is formed on the sidewall layer of polycrystalline silicon and over the insulating oxide film to get contact with the surface of the impurity-diffused region exposed by the contact hole. When the impurities are thermally diffused to make electrical contact between the polycrystalline silicon layer constituting the interconnection layer and the impurity-diffused region, the size of the impurity-diffused region for contact can be controlled such that it does not become larger than that of the contact hole. Thus, the impurity-diffused region for contact can be prevented from adversely affecting characteristics of the MOS transistor.
A contact structure for interconnection in FET devices, comprising:
A manufacturing method of a contact structure for interconnection in semiconductor devices, comprising the steps of:
An FET device comprising:
Dependencies are inferred from the claim text.