Protected erase voltage discharge transistor in a nonvolatile semiconductor memory

A nonvolatile flash electrically erasable programmable read only memory for storing digital data comprising:

• (A) a memory cell that can be programmed to store a bit of data;
• (B) a means for erasing the bit of data stored by the memory cell;
• (C) a transistor for reading the memory cell, wherein the transistor comprises:
• (1) a drain diffusion region coupled to a source diffusion region of the memory cell;
• (2) a source diffusion region of the transistor coupled to ground, wherein the source diffusion region of the transistor is implemented closer to the memory cell than the drain diffusion region;
• (3) a polysilicon gate coupled to a means for controlling whether the transistor is conducting wherein when the transistor is conducting, the source diffusion region of the memory cell is coupled to ground and a potential stored by parasitic capacitance associated with the memory cell is discharged through the transistor;
• (D) a first substrate tap, coupled to ground, located adjacent to the source of the transistor, to provide a discharge means for discharging the potential stored by the parasitic capacitance associated with the memory cell, wherein a diffusion distance between the transistor and the memory cell is minimized.