Integrated electrically adjustable analog transistor device

A CMOS integrated circuit comprising, in combination:

• a semiconductor substrate having a planar top surface;
• a first region of a first conductivity type located in said substrate and in contact with said planar top surface;
• second and third regions of a second conductivity type opposite said first conductivity type located in said first region in said substrate and in contract with said planar top surface, said second and said third regions of said second conductivity type forming the source and the drain, respectively, of a first MOS transistor;
• a separate fourth region of said second conductivity type located in said first region in said substrate and in contact with said planar top surface, said fourth region of said second conductivity type having a lower doping concentration than either of said second and third regions of said second conductivity type and forming a control junction;
• a fifth region of said second conductivity type located in said substrate and in contact with said planar top surface, said fifth region having a lower doping concentration than said fourth region of said second conductivity type;
• sixth and seventh regions of said first conductivity type located in said fifth region of said second conductivity type in said substrate and in contact with said planar top surface, said sixth and seventh regions of said first conductivity type forming the source and the drain respectively, of a second MOS transistor of complementary conductivity type to said first transistor;
• an insulating gate layer of substantially uniform thickness over each of said first, second, third, fourth, fifth, sixth and seventh regions of said first and second conductivity types in said substrate;
• conductive means connected to said fourth region of said second conductivity type for controlling the voltage on said control junction;
• conductive gate means over said insulating gate layer and spanning over said first, second, third, and fourth regions of said first and second conductivity types for controlling the threshold of said first MOS transistor by the combination of voltage on said control junction and charge injected at said drain of said first MOS transistor.