Two-level cache memory system

A cache memory system comprising:

• processing means for generating a virtual address;
• a primary cache memory, comprising:
• primary cache tag means containing a plurality of primary virtual tags, the primary cache tag means connected to receive at least a portion of the virtual address from the processing means and supply in response a corresponding primary cache virtual tag to the processing means;
• primary instruction cache means containing a plurality of instructions and a first plurality of virtual tags, the primary instructions and a first plurality of virtual tags, the primary instruction cache means connected to receive at least a portion of the virtual address from the processing means and supply in response a corresponding instruction from the plurality of instructions to the processing means;
• and
• primary data cache means containing a second plurality of primary virtual tags and a plurality of data units, the primary data cache means also connected to receive at least a portion of the virtual address from the processing means and in response to supply a corresponding data unit from the plurality of data units to the processing means;
• translation means connected to receive the virtual address form the processing and translate the virtual address into a physical address;
• and
• a secondary cache memory, comprising:
• secondary cache tag means containing a plurality of secondary virtual tags, the secondary cache tag means connected to receive at least a portion of the physical address from the translation means and supply in response a corresponding secondary virtual tag to the processing means;
• and
• secondary cache means containing a plurality of instructions and data units, the secondary cache means connected to receive at least a portion of the physical address from the translation means and supply in response a corresponding instruction or data unit from the plurality of instructions and data to the processing means;
• wherein the primary cache memory employs a virtual addressing scheme, thereby eliminating the need for address translation to access the primary cache memory.