Multilayered integrated circuit chip wiring arrangement

An integrated circuit chip, comprising:

• a substrate in which active circuits are formed;
• a lower layer of a plurality of parallel conductors formed over said substrate, a ratio of the thickness of the lower layer conductors to the separation between the lower layer conductors being within either of two ranges of values, one range having an upper limit of and including 0.25 and another range having a lower limit of and including 0.45;
• a first insulating layer of silicon dioxide over said lower layer conductors, a second insulating layer of silica over said first insulating layer, and a third insulating layer of silicon dioxide over said second insulating layer, said third insulating layer having troughs corresponding to spaces where the lower layer conductors are absent over said substrate and crests corresponding to spaces where the lower layer conductors are present over said substrate;
• and
• an upper layer of parallel conductors formed over said third insulating layer, the upper layer conductors extending in a direction normal to the length of said lower layer conductors, said upper layer conductors having a minimum step coverage of 50%.