US 5,296,733 AGranted

Hetero junction bipolar transistor with improved electrode wiring contact region

AssigneeHitachi, Ltd.

InventorsChushiroh Kusano, Hiroshi Masuda, Katsuhiko Mitani, Kazuhiro Mochizuki, Masaru Miyazaki, Masahiko Kawata, Susumu Takahashi

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Abstract

A hetero junction bipolar transistor provides a contact area an area between an emitter (or collector) electrode and a wiring formed on the electrode that is larger than that of the emitter (or collector). A variation in voltage applied to an emitter (or collector)-base junctions is prevented and a stable operation of the transistor is attained. In addition, when an etching operation is carried out, an insulation film is formed on a side part of a mask. A patterning of the emitter (or collector) is then carried out and thus an emitter (or collector) having a size approximate to that of the mask is formed.

Claims27

Dependent claims

A hereto junction bipolar transistor comprising:

a semi-insulative compound semiconductor substrate;
a first compound semiconductor layer having a first conductivity type formed on said semi-insulative compound semiconductor substrate;
a second compound semiconductor layer having a second conductivity type opposite to said first conductivity type formed on a top surface of said first compound semiconductor layer and having a predetermined shape;
a third compound semiconductor layer having said first conductivity type formed on a top surface of said second compound semiconductor layer and having a desired shape and composed of material differing from that of said second compound semiconductor layer;
a fourth compound semiconductor layer having said first conductivity type formed on a top surface of said third compound semiconductor layer and having a desired shape and composed of material differing from that of said third compound semiconductor layer;
an emitter pattern of conductive material formed on a top surface of said fourth compound semiconductor layer;
an electrode formed on a top surface of said emitter pattern;
a wiring formed on a top surface of said electrode;
and
an insulating film being disposed along side surfaces of said third compound semiconductor layer, said fourth compound semiconductor layer and said emitter pattern,
wherein said side surfaces of said third compound semiconductor layer, said fourth compound semiconductor layer, and said emitter pattern are substantially coplanar and
wherein an area of contact between said top surface of said electrode and said wiring is equal to or larger than area of said top surface of said fourth compound semiconductor layer.

9 more elements

A hetero junction bipolar transistor comprising:

a semi-insulative compound semiconductor substrate;
a first compound semiconductor layer having a first conductivity type formed on said semi-insulative semiconductor substrate;
a second compound semiconductor layer having said first conductivity type formed on a top surface of said first compound semiconductor layer and made of the same material as that of said first compound semiconductor layer;
a third compound semiconductor layer having a second conductivity type opposite to said first conductivity type formed on a top surface of said second compound semiconductor layer and having a desired shape and composed of the same material as that of said second compound semiconductor layer;
a fourth compound semiconductor layer formed on a top surface of said third compound semiconductor layer, having said first conductivity type and having a desired shape and composed of a material differing from that of said third compound semiconductor layer;
a fifth compound semiconductor layer formed on a top surface of said fourth compound semiconductor layer, having said first conductivity type and having a desired shape and composed of a material differing from that of said fourth compound semiconductor layer;
an electrode formed on a top surface of said fifth compound semiconductor layer;
a wiring formed on said electrode;
and
an insulating film being disposed along side surfaces of said third compound semiconductor layer, said fourth compound semiconductor layer, and said fifth semiconductor layer
wherein said third compound semiconductor layer, said fourth compound semiconductor layer, and said fifth compound semiconductor layer are substantially co-planar and
wherein an area of a contact between said top surface of electrode and said wiring is larger than an area of said top surface of said fourth compound semiconductor layer.

9 more elements

Dependencies are inferred from the claim text.