High value resistive load for an integrated circuit

An bipolar CMOS integrated circuit formed on a semiconductor substrate and having a highly resistive load structure comprising:

• a high resistivity semiconductor layer of a first conductivity type isolated from the semiconductor substrate by a first dielectric layer;
• the high resistivity semiconductor layer having defined therein heavily doped regions of said first conductivity type forming first and second source regions and a common drain region of first and second coupled MOS field effect transistors, the high resistivity semiconductor layer forming first and second resistive channel regions between the common drain region and the first and second source regions respectively;
• an overlying second dielectric layer;
• a conductive layer overlying the second dielectric layer and defining first and second gate electrodes overlying the first and second channel regions and isolated therefrom by the second dielectric layer;
• conductive means connecting the first and second gate electrodes to the respective first and second source regions to hold the gate to source voltage at zero, for biasing the transistor into a subthreshold high impedance state whereby the coupled transistors are operable together as a symmetrically "off" state device presenting a highly resistive load between contacts to first and second source regions.

A highly resistive load for a bipolar CMOS integrated circuit formed on a semiconductor substrate comprising:

• first and second accumulation mode thin film MOS FET transistors defined in a highly resistive semiconductor layer isolated from the semiconductor substrate, the transistors being coupled in series, each transistor having a resistively conductive channel region and a source region, and a common drain region;
• first and second terminal contacts being provided to the source of the respective first and second transistors,
• and each transistor having an isolated gate electrode tied to the respective source for holding the gate-source voltage at zero, for biasing the transistor into a subthreshold "off" state having a high impedance,
• the pair of coupled transistors being operable to provide a symmetrically OFF state device characterized by a high threshold voltage, a large subthreshold slope thereby providing a high resistance load between first and second terminal contacts which is linear over a bias range of +1.5V to -1.5V.