Integrated multicelled semiconductor switching device for high current applications

A semiconductor switching device comprising:

• a semiconductor substrate;
• a first thyristor in said semiconductor substrate for producing a predetermined current;
• a second thyristor in said semiconductor substrate, said second thyristor being located closer to an edge of said semiconductor than said first thyristor;
• and
• current exporting means, electrically connected between said first thyristor and said second thyristor, for exporting a portion of said predetermined current to said second thyristor,
• wherein said first thyristor comprises an anode, a first base region, a second base region and a first emitter region in said second base region, and
• wherein said current exporting means comprises a collector region in said second base region adjacent said first emitter region;
• export gating means, for electrically connecting said collector region to said first emitter region, in response to a first bias signal;
• and means for electrically connecting said collector region to said second thyristor.

A semiconductor switching device comprising:

• a semiconductor substrate;
• a first thyristor in said semiconductor substrate, comprising an anode, a first base region, a second base region and a first emitter region in said second base region and forming a P-N junction therewith;
• a collector region in said second base region adjacent said first emitter region;
• a cathode contact on said substrate, electrically connected to said first emitter region;
• a diverter region in said first base region, electrically connected to said cathode contact;
• a first field effect transistor of predetermined conductivity type having an active region in said second base region, between said first emitter region and said first base region;
• a second field effect transistor of opposite conductivity type from said first field effect transistor, and having an active region in said first base region, between said second base region and said diverter region;
• a third field effect transistor of said predetermined conductivity type having an active region in said second base region, between said collector region and said first emitter region;
• a second thyristor in said semiconductor substrate, said second thyristor comprising a second emitter region in said semiconductor substrate at a position closer to an edge of said semiconductor substrate than said first thyristor;
• and
• an electrical connector between said collector region and said second emitter region.

A multiple cell semiconductor switching device comprising:

• a semiconductor substrate having first and second opposing faces;
• a cathode contact on said first face;
• an anode contact on said second face;
• a plurality of first thyristor cells in said semiconductor substrate, each for producing a predetermined current, wherein each of said first thyristor cells includes a first emitter region of first conductivity type at said first face, contacting said cathode contact, and includes an anode region of second conductivity type at said second face, contacting said anode contact;
• a plurality of second thyristor cells in said semiconductor substrate, each for producing said predetermined current, said second thyristor cells being located closer to the interior of said semiconductor substrate than said first thyristor cells;
• a plurality of third thyristor cells in said semiconductor substrate, said third thyristor cells being located closer to an edge of said semiconductor substrate than said first thyristor cells and said second thyristor cells, wherein each of said third thyristor cells includes a second emitter region which is electrically disconnected from said cathode contact at said first face;
• and
• a plurality of current exporting means, each electrically connected between at least one of said first thyristor cells and at least one of said third thyristor cells and electrically disconnected from said cathode contact at said first face, for exporting a portion of said predetermined current from said first thyristor cells to said third thyristor cells, said second thyristor cells electrically connected in parallel with said first thyristor cells, between said cathode contact and said anode contact, and electrically connected in parallel with the series combination of said current exporting means and said third thyristor cells.

A multiple cell semiconductor switching device comprising:

• a semiconductor substrate;
• a plurality of first thyristor cells in said semiconductor substrate, each for producing a predetermined current;
• a plurality of second thyristor cells in said semiconductor substrate, each for producing said predetermined current, said second thyristor cells being located closer to the interior of said semiconductor substrate than said first thyristor cells;
• a plurality of third thyristor cells in said semiconductor substrate, said third thyristor cells being located closer to an edge of said semiconductor substrate than said first thyristor cells and said second thyristor cells;
• and
• a plurality of current exporting means, each electrically connected between at least one of said first thyristor cells and at least one of said third thyristor cells, for exporting a portion of said predetermined current from said first thyristor cells to said third thyristor cells, said second thyristor cells electrically connected in parallel with said first thyristor cells and electrically connected in parallel with the series combination of said current exporting means and said third thyristor cells,
• wherein each of said first thyristor cells comprises an anode, a first base region, a second base region and a first emitter region in said second base region and forming a P-N junction therewith, and
• wherein each of said current exporting means comprises a collector region in said second base region of a respective first thyristor cell, adjacent said respective first emitter region;
• export gating means, for electrically connecting said collector region to said respective first emitter region, in response to a bias signal;
• and means for electrically connecting said collector region to at least one of said plurality of third thyristor cells.

A multiple cell semiconductor switching device comprising:

• a semiconductor substrate;
• a plurality of first thyristor cells in said semiconductor substrate, each comprising an anode, a first base region, a second base region and a first emitter region in said second base region;
• a collector region in each of said second base regions adjacent the associated first emitter region;
• a cathode contact on said semiconductor substrate, electrically connected to each of said first emitter regions;
• a diverter region in each of said first base regions, electrically connected to the cathode contact;
• a plurality of first field effect transistors of predetermined conductivity type, a respective one of which has an active region between a respective first emitter region and a respective first base region of a respective first thyristor cell;
• a plurality of second field effect transistors of opposite conductivity type from said plurality of first field effect transistors, a respective one of which has an active region between a respective second base region and a respective diverter region of a respective first thyristor cell;
• a plurality of third field effect transistors of said predetermined conductivity type, a respective one of which has an active region between a respective collector region and a respective first emitter region of a respective first thyristor cell;
• a plurality of second thyristor cells in said semiconductor substrate, electrically connected in parallel with said plurality of first thyristor cells and located closer to the interior of said semiconductor substrate than said plurality of first thyristor cells;
• a plurality of third thyristor cells in said semiconductor substrate, each of which includes a second emitter region, said third thyristor cells being located closer to an edge of said semiconductor substrate than said first thyristor cells and said second thyristor cells;
• and
• a plurality of electrical connectors, each of which electrically connects at least one of said collector regions and at least one of said second emitter regions.