Low output capacitance, double-diffused field effect transistor

A low output-capacitance, double diffused field effect transistor comprising:

• a first conduction type semiconductor substrate having two major surfaces;
• a drain electrode provided on one of said major surfaces of said semiconductor substrate and connected to a drain terminal;
• well regions of a second conduction type in the other of said major surfaces of said semiconductor substrate formed by means of a double diffusion to have source regions of said first conduction type in each well region,
• said source regions being provided thereon with a source electrode connected to a source terminal;
• channel regions defined in a surface area of said well regions to be between a first conduction type semiconductor zone of said semiconductor substrate and said source regions;
• gate electrodes respectively provided above each of said channel regions with an insulating film interposed between said gate electrodes and said channel regions,
• said gate electrodes being connected through a first capacitance component means to a gate terminal;
• and
• a guard ring region of said second conduction type disposed in said first conduction type semiconductor zone to be outside said well regions including said channel regions, said guard ring region connected to said source electrode through a second capacitance component means.

A low output-capacitance, double diffused field effect transistor comprising:

• a first conduction type semiconductor substrate having two major surfaces;
• a drain electrode provided on one of said major surfaces of said semiconductor substrate and connected to a drain terminal;
• well regions of a second conduction type in the other of said major surfaces of said semiconductor substrate formed by means of a double diffusion to have source regions of said first conduction type in each well region,
• said source regions being provided thereon with a source electrode connected to a source terminal;
• channel regions defined in a surface area of said well regions to be between a first conduction type semiconductor zone of said semiconductor substrate and said source regions;
• gate electrodes respectively provided above each of said channel regions with an insulating film interposed between said gate electrodes and said channel regions,
• said gate electrodes being connected through at least a capacitance component means to a gate terminal, said capacitance component means comprising a pair of diodes connected mutually in inverse parallel relationship;
• and
• a guard ring region of said second conduction type disposed in said first conduction type semiconductor zone to be outside said well regions including said channel regions.

A solid-state relay comprising a light emitting means generating an optical signal upon receipt of an input signal, a photovoltaic means generating a photovoltaic force upon receipt of said optical signal emitted from said light emitting means, a power DMOSFET connected to said photovoltaic means and having a gate terminal, and means for driving said power DMOSFET from a first impedance state to a second impedance state with said photovoltaic force applied to said gate terminal;

• said power DMOSFET comprising a first conduction type semiconductor substrate having two major surfaces, a drain electrode provided on one of said major surfaces of said semiconductor substrate and connected to a drain terminal, well regions of a second conduction type and source regions of said first conduction type respectively formed by means of a double diffusion in the other of said major surfaces of said semiconductor substrate, said source regions being provided thereon with a source electrode connected to a source terminal, channel regions defined in a surface area of said well regions to be between a first conduction type semiconductor zone of said semiconductor substrate and said source regions, gate electrodes respectively provided above each of said channel regions with an insulating film interposed between said gate electrodes and said channel regions, said gate electrodes being connected through a first capacitance component means to said gate terminal;
• and a guard ring region of said second conduction type disposed in said first conduction type semiconductor zone to be outside said well regions including said channel regions, said guard ring region being connected to said source regions through a second capacitance component means.