US 5,296,092 A · Planarization method for a semiconductor substrate

Abstract

Disclosed is a method for planarizing the insulating layer formed on a semiconductor substrate without forming voids. An insulating layer is coated on a semiconductor substrate on which a metal wiring layer has been previously formed, and then a resist layer serving as a sacrificial layer is formed on the insulating layer. Etching the sacrificial layer provides a sacrificial residue on the insulating layer between portions of the metal wiring layer. After an upper portion of the insulating layer is istropically etched, the insulating layer and sacrificial residue are anisotropically etched. An insulating layer thus-obtained has a good profile so that a planarized insulating interlayer free of voids is obtained by an additional etch-back process using a second sacrificial layer. Consequently, a subsequent second metal wiring formation or lithography process can be easily carried out.

Claims10

Dependent claims

A method for the planarization of a semiconductor substrate comprising the steps of:

(a) coating an insulating layer on a semiconductor substrate on which a metal wiring layer has been previously formed;
(b) forming a sacrificial layer on said insulating layer;
(c) etching said sacrificial layer forming sacrificial residues on said insulating layer between portions of said metal wiring layer;
(d) isotropically etching said insulating layer;
and
(e) anisotropically etching said sacrificial residues and said isotropically etched insulating layer simulataneously.

3 more elements

Dependencies are inferred from the claim text.

Planarization method for a semiconductor substrate

Life of this patent

Planarization method for a semiconductor substrate

Life of this patent

Abstract

Claims10