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US 5,294,822 AGranted
Polycide local interconnect method and structure
AssigneeTexas Instruments Incorporated
InventorDouglas P. Verrett
Life of this patent
Estimating the term…
Abstract
A local interconnect comprises a doped, silicided amorphous or polysilicon layer 28. One interconnect 34, 35 extends between an isolated gate contact 60 and a source and drain 61 of an NMOS transistor 42. Another local interconnect 34,37 extends between a source and a drain 62, 63 of CMOS transistors.
Claims20
A semiconductor device, comprising:
- a first transistor with first and second terminals and an insulated gate for controlling current between the first and second terminals;
- an isolation region adjoining one of said terminals;
- a second gate disposed on said isolation region;
- a layer of non-monocrystalline silicon above and adjacent an upper surface of said isolation region, said one of said terminals and said second gate;
- and
- a silicide layer above and adjacent said layer of non-monocrystalline silicon.
3 more elements
A semiconductor device, comprising:
- a first transistor with first and second terminals and an insulated gate for controlling current between the first and second terminals;
- an isolation region adjoining one of said terminals;
- a second gate disposed on said isolation region;
- a layer of non-monocrystalline silicon in contact with said one of said terminals and said second gate;
- a silicide layer in contact with said non-monocrystalline silicon layer, said silicide layer covering side surfaces of said non-monocrystalline silicon layer;
- a second isolation region spacing a second transistor from said first transistor;
- and
- a second non-monocrystalline silicon layer extending from the other terminal of the first transistor, over the second isolation region to a terminal of the second transistor.
5 more elements
A CMOS device, comprising:
- an NMOS and a PMOS transistor, each transistor having a source, a gate and a drain;
- a first isolation region separating the NMOS transistor from the PMOS transistor;
- a second isolation region adjoining the source or the drain of the NMOS transistor;
- a second gate disposed on said second isolation region;
- a non-monocrystalline silicon layer above and adjacent an upper surface of said second isolation region, said source or said drain and said second gate;
- and
- a silicide layer above and adjacent said non-monocrystalline silicon layer.
4 more elements
A CMOS device, comprising:
- an NMOS and a PMOS transistor, each transistor having a source, a gate and a drain;
- a first isolation region separating the NMOS transistor from the PMOS transistor;
- a second isolation region adjoining the source or the drain of the NMOS transistor;
- a second gate disposed on said second isolation region;
- a non-monocrystalline silicon layer in contact with said source or said drain and at least a top surface of said second gate;
- a silicide layer in contact with said non-monocrystalline silicon layer, said silicide layer covering side surfaces of said non-monocrystalline layer;
- and
- a second non-monocrystalline silicon layer extending from the other of the source or the drain of the NMOS transistor, over the first isolation region to a source or drain of the PMOS transistor.
5 more elements
Dependencies are inferred from the claim text.