US 5,294,816 AGranted

Unit cell arrangement for emitter switched thyristor with base resistance control

AssigneeNorth Carolina State University at Raleigh

InventorsMallikarjunaswamy S. Shekar, Mahalingam Nandakumar, Bantval J. Baliga

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Abstract

An emitter switched thyristor with base resistance control for preventing parasitic latch-up includes a P-N-P-N main thyristor with an N.sup.+ floating emitter for MOS-gated controlled turn-on and a lateral P-channel MOSFET for shunting hole current in a second base region to a P.sup.+ diverting region electrically connected to the cathode. The P-channel MOSFET is enabled by the application of a negative gate voltage to form a P-type inversion layer between the second base region and the P.sup.+ diverter region, thus reducing the resistance between the cathode and the second base region and raising the holding current of the emitter switched thyristor to above the operating current level. The formation of an alternative current path to the cathode has the further effect of reducing the forward bias across the base-emitter junction of an adjacent parasitic thyristor to thereby prevent the sustained regenerative action of the parasitic thyristor.

Claims12

Dependent claims

A semiconductor switching device comprising:

a semiconductor substrate having a face;
a first thyristor in said semiconductor substrate, said first thyristor comprising an anode, a first base region of first conductivity type on said anode and extending to said face, a second base region of second conductivity type, opposite said first conductivity type, in said first base region at said face, and a first floating emitter region of first conductivity type in said second base region at said face;
a first emitter region of first conductivity type in said semiconductor substrate at said face, adjacent said first floating emitter region;
a second thyristor in said semiconductor substrate, adjacent said first thyristor, said second thyristor comprising said anode, said first base region, a third base region of second conductivity type in said first base region at said face and adjacent said second base region, and a second floating emitter region of first conductivity type in said third base region at said face;
a second emitter region of first conductivity type in said semiconductor substrate at said face, adjacent said second floating emitter region;
first gating means at said face, between said second base region and said third base region, for electrically connecting said first floating emitter region and said second floating emitter region to said first base region in response to a first bias signal;
second gating means at said face, between said first floating emitter region and said first emitter region, for electrically connecting said first emitter region to said first floating emitter region, to thereby provide electron conduction between said first emitter region and said first floating emitter region in a first direction, in response to said first bias signal;
third gating means at said face, between said second floating emitter region and said second emitter region, for electrically connecting said second emitter region to said second floating emitter region, to thereby provide electron conduction between said second emitter region and said second floating emitter region in a second direction, opposite said first direction, in response to said first bias signal;
a diverter region of second conductivity type in said semiconductor substrate at said face;
diverting means for electrically connecting said second base region and said third base region to said diverter region in response to a second bias signal, to thereby provide hole conduction between said second and third base regions and said diverter region in a third direction, orthogonal to said first and said second directions.

7 more elements

A semiconductor switching device comprising:

a semiconductor substrate having a face;
a thyristor in said semiconductor substrate, said thyristor comprising an anode, a first base region of first conductivity type on said anode, a second base region of second conductivity type, opposite said first conductivity type, in said first base region, a third base region of second conductivity type in said first base region, a first floating emitter region of first conductivity type in said second base region, a second floating emitter region of first conductivity type in said third base region;
a first emitter region of first conductivity type in said semiconductor substrate at said face, said first emitter region forming a p-n junction with said second base region;
a second emitter region of first conductivity type in said semiconductor substrate at said face, said second emitter region forming a p-n junction with said third base region;
a diverter region of second conductivity type in said semiconductor substrate;
diverting means, in said semiconductor substrate, for electrically connecting said second base region and said third base region to said diverter region in response to a first bias signal, to thereby provide hole conduction between said second and third base regions and said diverter region in a first direction;
turn-on gating means, in said semiconductor substrate, for electrically connecting said first emitter region to said first base region and for electrically connecting said second emitter region to said first base region, so that electron conduction occurs in opposing directions, orthogonal to said first direction, in said first floating emitter region and said second floating emitter region, respectively, in response to a second bias signal.

4 more elements

Dependencies are inferred from the claim text.