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US 5,294,561 AGranted
Method for manufacturing highly-integrated stacked capacitor
AssigneeNEC Corporation
InventorTakaho Tanigawa
Life of this patent
Estimating the term…
Abstract
An impurity doped region is formed in a semiconductor substrate, and an insulating layer is formed thereon. A conductive layer is formed and is patterned by a photolithography process Then, a conductive sidewall is formed inside of the conductive layer. The insulating layer is etched with a mask of the conductive sidewall and the conductive layer to create a contact hole leading to the impurity doped region. A capacitor lower electrode layer is deposited within the contact hole. Thus, a capacitor insulating layer and a capacitor upper electrode layer are formed, to obtain a stacked capacitor.
Claims6
A method for manufacturing a stacked capacitor, comprising the steps of:
- forming an impurity doped region within a semiconductor substrate, the conductivity type of said impurity doped region being opposite to that of said semiconductor substrate;
- forming an insulating layer on said semiconductor substrate;
- forming a conductive layer on said insulating layer;
- patterning said conductive layer to create an opening therein, said opening being located over said impurity doped region;
- forming a conductive sidewall along the inside of the opening of said conductive layer;
- patterning said insulating layer with a mask of said conductive layer and said conductive sidewall to create a contact hole leading to said impurity doped region;
- forming a capacitor lower electrode layer, said conductive lower electrode layer being electrically connected to said impurity doped region, said conductive layer and said conductive sidewall;
- forming a capacitor insulating layer on said capacitor lower electrode layer;
- and
- forming a capacitor upper electrode layer on said capacitor insulating layer.
7 more elements
A method for manufacturing a semiconductor memory device comprising the steps of:
- forming a thick insulating layer on a semiconductor substrate of a first conductivity type;
- forming a gate insulating layer on said semiconductor substrate;
- forming a gate electrode layer on said gate insulating layer;
- forming a source region and a drain region by introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said thick insulating layer and said gate electrode layer;
- forming a first insulating layer on said semiconductor substrate, said thick insulating layer and said gate electrode layer;
- forming a conductive layer on said first insulating layer;
- patterning said conductive layer to create an opening therein said opening being located over said drain region;
- forming a conductive sidewall along the inside of the opening of said conductive layer;
- patterning said first insulating layer with a mask of said conductive layer and said conductive sidewall to create a contact hole leading to said drain region;
- forming a capacitor lower electrode layer, said conductive lower electrode layer being electrically connected to said drain region, said conductive layer and said conductive sidewall;
- forming a capacitor insulating layer said capacitor lower electrode layer;
- forming a capacitor upper electrode layer on said capacitor insulating layer;
- patterning said capacitor upper electrode layer, said capacitor insulating layer and said capacitor lower electrode layer;
- forming a second insulating layer on said capacitor upper electrode and said first insulating layer;
- patterning said second insulating layer and said first insulating layer to create a contact hole leading to said source region;
- and
- forming a bit line electrode layer to be connected to said source region.
14 more elements
A method for manufacturing a semiconductor memory device comprising the steps of:
- forming a thick insulating layer on a semiconductor substrate of a first conductivity type;
- forming a gate insulating layer on said semiconductor substrate;
- forming a gate electrode layer on said gate insulating layer;
- forming a source region and a drain region by introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said thick insulating layer and said gate electrode layer;
- forming an first insulating layer on said semiconductor substrate, said thick insulating layer and said gate electrode layer;
- patterning said first insulating layer to create a contact hole leading to said source region;
- forming a bit line electrode layer to be connected to said source region;
- forming a second insulating layer on said bit line electrode layer and said first insulating layer;
- forming a conductive layer on said second insulating layer;
- patterning said conductive layer to create an opening therein, said opening being located over said drain region;
- forming a conductive sidewall along the inside of the opening of said conductive layer;
- patterning said first and second insulating layers with a mask of said conductive layer and said conductive sidewall to create a contact hole leading to said drain region;
- forming a capacitor lower electrode layer, said conductive lower electrode layer being electrically connected to said drain region, said conductive layer and said conductive sidewall;
- forming a capacitor insulating layer on said capacitor lower electrade layer;
- forming a capacitor upper electrode layer on said capacitor insulating layer.
12 more elements
Dependencies are inferred from the claim text.