Electrically reprogrammable EPROM cell with merged transistor and optiumum area

Abstract

A novel nonvolatile memory cell structure is provided using a non-self aligned CMOS process with two independent N+ implants using a two or a three polysilicon layer technology that allows in-circuit electrical erase and reprogramming together with reduction in cell size requirement. The novel memory cell is implemented with a merged transistor structure having an access transistor and a programmable transistor. The memory cell is constructed by having the control gate, formed of a first polysilicon layer, covering a portion of the channel length between drain and source to form the access portion of the merged transistors, and a floating gate formed of a second polysilicon layer overlapping a second portion of the channel length to form the programmable transistor portion of the merged transistor. Such merged transistor structure is equivalent to two transistors in series, a programmable transistor in series with an access transistor. A memory cell structure described in accordance with this invention allows a reduction of the portion of the floating gate covering the programmable transistor portion of the channel length. This results in a reduction in the floating gate to substrate capacitance (C.sub.FB) thereby improving the programming coupling ratio and reducing the overall cell size.

Dependencies are inferred from the claim text.