SOT CMOS device having differentially doped body extension for providing improved backside leakage channel stop

A field effect transistor device comprising:

• a dielectric substrate;
• a field effect transistor structure disposed on said dielectric substrate, said field effect transistor structure including a body region of a first conductivity type formed on a first surface portion of said dielectric substrate, a source region of a second conductivity type formed on a second surface portion of said dielectric substrate contiguous with said first surface portion and forming a source/body junction with said body region, said source/body junction having a first length along said body region, a drain region of said second conductivity type formed on a third surface portion of said dielectric substrate, spaced apart from said second surface portion by said first surface portion therebetween, and being contiguous with said first surface portion and forming a drain/body junction with said body region, said drain/body junction having a second length along said body region, and a gate layer insulated from and overlying said body region for inducing therein a channel region between said source and drain regions, and wherein said body region extends beyond said source and drain regions as at least one body extension region underlying said gate layer, and wherein a portion of said at least one body extension region underlying said gate layer has an impurity distribution profile that is increased along the interface of said portion of said at least one body extension region with said dielectric substrate relative to a top surface of said at least one body extension region.

A mesa field effect transistor architecture comprising:

• a dielectric support substrate;
• a mesa field effect transistor structure disposed on said dielectric support substrate, said mesa field effect transistor structure including a body mesa region of a first conductivity type formed on a first surface portion of said dielectric support substrate, a source mesa region of a second conductivity type formed on a second surface portion of said dielectric support substrate contiguous with said first surface portion and forming a source/body junction with a first sidewall of said mesa body region, a drain mesa region of said second conductivity type formed on a third surface portion of said dielectric support substrate, spaced apart from said second surface portion by said first surface portion therebetween, and being contiguous with said first surface portion and forming a drain/body junction with a second sidewall of said body region, and a gate layer overlying said mesa body region for inducing therein a channel region between said source and drain mesa regions, said body mesa region extending beyond said source and drain mesa regions as at least one extension mesa region underlying said gate layer, and wherein a first end portion of said at least one extension mesa region underlying said gate layer has an impurity concentration greater than the impurity concentration of a portion of said body mesa region disposed between said source and drain mesa regions, so as to form a mesa sidewall channel stop, and wherein a portion of said at least one extension mesa region underlying said gate layer between said first end portion thereof and said channel region has an impurity concentration profile that is increased along the interface of said portion of said at least one extension mesa region with said dielectric support substrate relative to a top surface of said at least one extension mesa region.

A method of inhibiting radiation-induced leakage along an interface of an N-channel field effect transistor with an underlying dielectric substrate upon which said N-channel field effect transistor is disposed, said N-channel field effect transistor including a P-type body region disposed on a first surface portion of said dielectric substrate, an N-type source region disposed on a second surface portion of said dielectric substrate contiguous with said first substrate portion and forming a source/body PN junction with said P-type body region, said source/body PN junction having a first length along said P-type body region, an N-type drain region formed on a third surface portion of said dielectric substrate, spaced apart from said second surface portion by said first surface portion therebetween, and being contiguous with said first surface portion and forming a drain/body PN junction with said P-type body region, said drain/body PN junction having a second length along said P-type body region, and a gate layer insulated from and overlying said P-type body region for inducing therein an N-channel region between said source and drain regions, comprising the steps of:

• (a) extending said P-type body region beyond said source and drain regions as at least one P-type extension region underlying said gate layer;
• and
• (b) causing a portion of said at least one P-type extension region underlying said gate layer to have an impurity distribution profile that is increased along the interface of said portion of said at least one P-type extension region with said dielectric substrate relative to a top surface of said at least one P-type extension region.