Method for planarizing semiconductor structure using subminimum features
AssigneeInternational Business Machines Corporation
InventorsJohn E. Cronin, Howard S. Landis
Life of this patent
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Abstract
The invention provides a method for planarizing over a recessed area of a semiconductor structure. The method involves the creation of a series of subminimum (i.e. 50 to 500 Angstroms thick) silicon pillars extending vertically upward from the base of a wide trench, and oxidizing the pillars. When the substrate is covered with a conformal CVD oxide, the pillars prevent the formation of a single deep depression above the trench.
Claims21
A method of planarizing over a recessed area of a semiconductor structure, said method comprising:
- a) forming pillars and a recessed area on a semiconductor structure, said semiconductor structure having a surface thereof adjacent said recessed area, said pillars being formed within said recessed area, wherein said pillars are less than the minimum feature size that can be formed for said semiconductor structure;
- b) depositing a layer of fill over said pillars, said recessed area, and said surface, said pillars preventing substantial depression of said layer of fill overlying said recessed area relative to said surface;
- and
- c) planarizing said layer of fill by chemical-mechanical polishing wherein a second surface of said planarized layer of fill is thereby substantially planar with said surface of said semiconductor structure.
A method of planarizing over a recessed area of a semiconductor structure, said method comprising:
- a) forming pillars and a recessed area on a semiconductor structure, said semiconductor structure having a surface thereof adjacent said recessed area, said pillars being formed within said recessed area;
- b) depositing a layer of fill over said pillars, said recessed area, and said surface, wherein said pillars are formed with pre-selected spacing and cross-sectional dimensions so as to prevent substantial depression of said layer of fill overlying said recessed area, and wherein said pre-selected spacing is such that the density of said pillars comprises one to ten pillars per square micron;
- and
- c) planarizing said layer of fill by chemical-mechanical polishing wherein a second surface of said planarized layer of fill is thereby substantially planar with said surface of said semiconductor structure.
Dependencies are inferred from the claim text.