Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors

A process for fabricating a semiconductor wafer to form a memory array and peripheral area, the array comprising nonvolatile memory devices employing floating gate transistors of a first conductivity type, the peripheral area comprising first and second conductivity type CMOS transistors, the method comprising the following steps:

• providing field and gate insulating layers on a semiconductor wafer, and defining an array area and an area peripheral to the array area for formation of first conductivity type nonvolatile memory devices in the array and formation of first and second conductivity type CMOS transistors in the peripheral area, the peripheral area comprising first and second peripheral areas, the first and second conductivity type CMOS transistors to be formed in the first and second peripheral areas respectively, such providing and defining comprising N-well and P-well formation, such formation comprising:
• a) oxidizing the wafer to create a first silicon dioxide layer thereon;
• b) subjecting the wafer to a blanket P-well implant;
• c) masking future P-well regions with photoresist;
• d) etching away those portions of the first silicon dioxide layer that are not subjacent photoresist;
• e) recessing those portions of the substrate that are not subjacent photoresist;
• f) subjecting the wafer to an N-well implant;
• g) stripping photoresist;
• and h) subjecting the wafer to a high-temperature substrate drive step to drive atoms of the P-well implant and atoms of the N-well implant to diffuse deeper into the substrate;
• providing a first layer of conductive material atop the insulating layers;
• providing a dielectric layer atop the first conductive layer for use in floating gate transistors within the array;
• etching the dielectric layer and first conductive material from the peripheral area, and leaving dielectric layer and first conductive material in the array;
• after etching the dielectric layer and first conductive material from the peripheral area, providing a second layer of conductive material atop the wafer which covers the peripheral area and dielectric layer of the array;
• patterning and etching the first conductive, second conductive and dielectric layers of the array and second conductive layer of the peripheral area to form transistor gates for the peripheral second conductivity type CMOS transistors, and to cover the array and first peripheral area;
• first doping exposed areas of the second peripheral area with second conductivity type material, the second layer of conductive material in the array and first peripheral area masking the array and first peripheral area from implantation during the first doping;
• after doping the second peripheral area, patterning and etching the second conductive layer in the peripheral area to form transistor gates for the first conductivity type CMOS transistors in the first peripheral area, and to cover the array;
• after doping the second peripheral area, patterning and etching the first conductive, second conductive and dielectric layers of the array to form gate regions of floating transistors;
• after doping the second peripheral area and after patterning and etching only one of the array or first peripheral area, second doping exposed areas of the one of the array or first peripheral area with first conductivity type material while the second peripheral area and other of the array or first peripheral area are masked, the other of the array or first peripheral area being masked by unpatterned second conductive layer without the use of photoresist during such second doping;
• and
• after the first and second dopings, common doping exposed areas of the array and first peripheral area with first conductivity type material in the same step while the second peripheral area is masked.

A process for fabricating a semiconductor wafer to form a memory array and peripheral area, the array comprising nonvolatile memory devices employing floating gate transistors of a first conductivity type, the peripheral area comprising first and second conductivity type CMOS transistors, the method comprising the following steps:

• providing field and gate insulating layers on a semiconductor wafer, and defining an array area and an area peripheral to the array area for formation of first conductivity type nonvolatile memory devices in the array and formation of first and second conductivity type CMOS transistors in the peripheral area, the peripheral area comprising first and second peripheral areas, the first and second conductivity type CMOS transistors to be formed in the first and second peripheral areas respectively, such providing and defining comprising N-well and P-well formation, such formation comprising:
• a) oxidizing the wafer to create a first silicon dioxide layer thereon;
• b) subjecting the wafer to a blanket P-well implant;
• c) masking future P-well regions with photoresist;
• d) etching away those portions of the first silicon dioxide layer that are not subjacent photoresist;
• e) recessing those portions of the substrate that are not subjacent photoresist;
• f) subjecting the wafer to an N-well implant;
• g) stripping photoresist;
• and h) subjecting the wafer to a high-temperature substrate drive step to drive atoms of the P-well implant and atoms of the N-well implant to diffuse deeper into the substrate;
• providing a first layer of conductive material atop the insulating layers;
• providing a dielectric layer atop the first conductive layer for use in floating gate transistors within the array;
• etching the dielectric layer and first conductive material from the peripheral area, and leaving dielectric layer and first conductive material in the array;
• after etching the dielectric layer and first conductive material from the peripheral area, providing a second layer of conductive material atop the wafer which covers the peripheral area and dielectric layer of the array;
• patterning and etching the first conductive, second conductive and dielectric layers of the array and second conductive layer of the peripheral area to form gate regions of floating gate transistors in the array, and to cover the peripheral area;
• patterning and etching the second conductive layer in the peripheral area to form transistor gates for the first conductivity type CMOS transistors in the first peripheral area, and to cover the second peripheral area;
• after patterning and etching the array to form floating gate transistors and after patterning and etching the peripheral area to form transistor gates for the first conductivity type CMOS transistors, masking the second peripheral area with the second conductive layer without the use of photoresist and common doping exposed areas of the array and first peripheral area with first conductivity type material in the same step;
• after patterning the array and first peripheral area, patterning and etching the second conductive layer in the second peripheral area to form transistor gates for the second conductivity type CMOS transistors in the second peripheral area;
• and
• after patterning and etching the second peripheral area, doping exposed areas of the second peripheral area with second conductivity type material while the array and first peripheral area are masked.

A process for fabricating a semiconductor wafer to form a memory array and peripheral area, the array comprising nonvolatile memory devices employing floating gate transistors of a first conductivity type, the peripheral area comprising first and second conductivity type CMOS transistors, the method comprising the following steps:

• providing field and gate insulating layers on a semiconductor wafer, and defining an array area and an area peripheral to the array area for formation of first conductivity type nonvolatile memory devices in the array and formation of first and second conductivity type CMOS transistors in the peripheral area, the peripheral area comprising first and second peripheral areas, the first and second conductivity type CMOS transistors to be formed in the first and second peripheral areas respectively, such providing and defining comprising N-well and P-well formation, such formation comprising:
• a) oxidizing the wafer to create a first silicon dioxide layer thereon;
• b) subjecting the wafer to a blanket P-well implant;
• c) masking future P-well regions with photoresist;
• d) etching away those portions of the first silicon dioxide layer that are not subjacent photoresist;
• e) recessing those portions of the substrate that are not subjacent photoresist;
• f) subjecting the wafer to an N-well implant;
• g) stripping photoresist;
• and h) subjecting the wafer to a high-temperature substrate drive step to drive atoms of the P-well implant and atoms of the N-well implant to diffuse deeper into the substrate;
• providing a first layer of conductive material atop the insulating layers;
• providing a dielectric layer atop the first conductive layer for use in floating gate transistors within the array;
• etching the dielectric layer and first conductive material from the peripheral area, and leaving dielectric layer and first conductive material in the array;
• after etching the dielectric layer and first conductive material from the peripheral area, providing a second layer of conductive material atop the wafer which covers the peripheral area and dielectric layer of the array;
• patterning and etching the first conductive, second conductive and dielectric layers of the array and second conductive layer of the peripheral area to form transistor gates for the peripheral second conductivity type CMOS transistors, and to cover the array and first peripheral area;
• doping exposed areas of the second peripheral area with second conductivity type material, the second layer of conductive material in the array and first peripheral area masking the array and first peripheral area from implantation during the doping;
• after doping the second peripheral area, patterning and etching the second conductive layer in the peripheral area to form transistor gates for the first conductivity type CMOS transistors in the first peripheral area, and to cover the array;
• after doping the second peripheral area, patterning and etching the first conductive, second conductive and dielectric layers of the array to form gate regions of floating transistors;
• and
• common doping exposed areas of the array and first peripheral area with first conductivity type material in the same step while the second peripheral area is masked.