Semiconductor memory cell and memory array with inversion layer

A memory cell having five layers of polysilicon fabricated on a substrate, said memory cell comprising:

• a first polysilicon gate layer comprising an inversion drain gate and a separate inversion source gate, each of said inversion gates being disposed above said substrate such that an inversion drain and an inversion source are respectively produced in said substrate beneath said inversion drain gate and said inversion source gate when potentials are applied thereto, said inversion source and said inversion drain defining a channel region in said substrate;
• a second polysilicon gate layer comprising an insolation plate for isolating said cell, said isolation plate overlying a portion of said substrate and said first polysilicon gate layer;
• a third polysilicon gate layer comprising an electrically isolated floating gate, said third gate layer being isolated from said substrate, said first gate layer and said second gate layer, said third gate layer overlapping at least a portion of said second gate layer and at least a portion of said channel region in said substrate;
• a fourth polysilicon gate layer comprising a program gate, said fourth gate layer being isolated from said substrate, said first gate layer, said second gate layer and said third gate layer, said fourth polysilicon gate layer overlapping at least a portion of said third gate layer;
• a fifth polysilicon gate layer comprising an access gate, said fifth gate layer being isolated from said substrate, said first gate layer, said second gate layer, said third gate layer and said fourth gate layer, said fifth polysilicon gate layer being aligned at least partially over said substrate channel region;
• and
• wherein application of a potential to said fourth gate layer and simultaneous grounding of said second gate layer establishes a cell write cycle in which said third gate layer may be selectively charged positive or negative by respectively grounding or applying a potential to said inversion drain gate.

A memory array fabricated on a substrate, said array comprising:

• a plurality of drain lines;
• a plurality of gate regions, each gate region being disposed above said substrate adjacent one of said plurality of drain lines, each of said plurality of gate regions including a floating gate;
• a plurality of inversion source gates, each said inversion source gate being disposed above said substrate adjacent to multiple ones of said plurality of gate regions, each of said plurality of inversion source gates inducing an inversion source line in said substrate upon application of a potential thereto, each said inversion source line defining a channel region in said substrate extending to an associated one of said plurality of drain lines, each of said defined channel regions being at least partially disposed under the floating gate of an associated gate region;
• and
• wherein during a read cycle said inversion source lines are established to pass charge from selected ones of said gate regions to their associated drain lines, and during a write cycle inversion source lines are removed to inject charge from selected inversion source gates into the floating gates of the associated gate regions.

A memory cell fabricated on a substrate, said memory cell comprising:

• a drain line;
• a gate region, said gate region being disposed above said substrate adjacent said drain line, said gate region including a floating gate;
• an inversion source gate, said inversion source gate being disposed above the substrate adjacent the gate region, said inversion source gate inducing an inversion source line in said substrate upon application of a potential thereto, said inversion source line defining a channel region in said substrate extending to said drain line, said defined channel region being partially disposed under the floating gate of said gate region;
• and
• wherein during a read cycle an inversion source line is established to pass charge from said gate region to said drain line, and during a write cycle an inversion source line is removed to inject charge from the inversion source gate into the floating gate of the gate region.