US 5,291,438 A · Transistor and a capacitor used for forming a vertically stacked dynamic random access memory cell

Abstract

A transistor and a capacitor is used to provide, in one form, a dynamic random access memory (DRAM) cell (10). The capacitor of cell (10) lies within a substrate (12). The capacitor has a first capacitor electrode (16) and a second capacitor electrode (20). A dielectric layer (18) is formed as an inter-electrode capacitor dielectric. A first transistor current electrode (36) is formed overlying and electrically connected to the first capacitor electrode (16). A channel region (38) is formed overlying the first transistor current electrode (36). A second transistor current electrode (40) is formed overlying the channel region (38). A conductive layer (30) is formed laterally adjacent the channel region (38) and isolated from the substrate (12) by dielectric layers (22 and 28). A conductive layer (30) functions as a gate electrode for the transistor and a sidewall dielectric (34) functions as a gate dielectric. The combination of a cylindrical dual-sidewall surface area capacitor for a large capacitance, along with a vertical transistor physically overlying the capacitor, forms a very dense and efficient DRAM structure.

Claims21

Dependent claims

A dynamic memory cell comprising:

a substrate having a surface;
a trench region having an outer trench sidewall and an inner trench sidewall wherein the outer trench sidewall faces the inner trench sidewall within the substrate to form a cylindrical trench region;
a trench capacitor having both a first capacitor electrode and a second capacitor electrode, the trench capacitor being formed within the trench region, the trench capacitor having an exposed base layer region lying within the inner trench sidewall of the trench region, the exposed base layer region being physically separated from the outer trench sidewall;
and
a transistor overlying the surface of the substrate and substantially directly overlying the trench capacitor, the transistor having a first current electrode that substantially overlies a second current electrode, the transistor being coupled to the trench capacitor by a conductive region.

2 more elements

A capacitor comprising:

a substrate having a surface;
a trench region within the substrate, the trench region having a trench sidewall which lies below the surface of the substrate and a trench bottom surface which lies below the surface of the substrate;
a conductive region within the trench, the conductive region having a periphery which is laterally separated from the trench sidewall, the conductive region being electrically coupled to the trench bottom surface wherein the periphery has a surface which faces the trench sidewall;
a first capacitor electrode laterally adjacent the trench sidewall, adjacent the trench bottom surface, and laterally adjacent the periphery of the conductive region, the first capacitor electrode being at least partially formed below the surface of the substrate;
a capacitor dielectric region overlying the first capacitor electrode;
and
a second capacitor electrode overlying the first capacitor electrode, the second capacitor electrode being isolated from the first capacitor electrode by the capacitor dielectric region and being at least partially formed below the surface of the substrate.

4 more elements

A dynamic memory cell comprising:

a substrate having a surface;
a trench capacitor within the substrate and having a base layer;
and
a transistor overlying the surface of the substrate and substantially overlying the trench capacitor, the transistor having a first current electrode that substantially overlies a channel region wherein the channel region overlies a second current electrode of the transistor, the transistor comprising:
a first dielectric layer overlying the substrate;
a control electrode conductive layer overlying the first dielectric layer;
a second dielectric layer overlying the control electrode conductive layer;
an opening through the first dielectric layer, the control electrode conductive layer, and the second dielectric layer which exposes the base layer of the trench capacitor, the opening defining a sidewall of the control electrode conductive layer;
a sidewall dielectric laterally adjacent the sidewall of the control electrode conductive layer;
and
a first conductive region within the opening, the first conductive region having a first portion which functions as a first current electrode, the first portion being laterally adjacent the first dielectric layer and electrically connected to the base layer, the first conductive region having a second portion which functions as a channel region, the second portion being laterally adjacent the sidewall dielectric and overlying the first current electrode, and the first conductive region having a third portion which functions as a second current electrode, the third portion being laterally adjacent the second dielectric layer and overlying the channel region.

8 more elements

Dependencies are inferred from the claim text.

Transistor and a capacitor used for forming a vertically stacked dynamic random access memory cell

Life of this patent

Transistor and a capacitor used for forming a vertically stacked dynamic random access memory cell

Life of this patent

Abstract

Claims21