MOS device having reduced gate-to-drain capacitance
AssigneeFuji Electric Co., Ltd.
InventorTakeyoshi Nishimura
Life of this patent
Estimating the term…
Abstract
A metal-oxide-semiconductor (MOS) device designed to achieve reduced gate-to-drain capacitance is disclosed. The device has gate-electrode layer consisting of alternating polarity regions, such that regions of the gate-electrode layer not involved in channel operations have a conductivity type different from the conductivity type of the gate-electrode-layer regions actually involved in channel operations. Since the alternating conductivity regions form a capacitance in series to the gate-to-drain capacitance, the gate-to-drain capacitance of the device is reduced. An embodiment of the invention also incorporates increased-thickness regions of the gate-oxide film, which regions are disposed over semiconductor areas at which no channel operation occurs.
Claims6
A metal-oxide-semiconductor device comprising:
- a first semiconductor region of a first conductive type having a first surface and a second surface;
- a plurality of second regions of a second conductive type at said first surface of said first semiconductor region;
- a third region of said first conductive type in each of said second regions;
- whereby a plurality of channel regions are formed between said third region and said first surface of said first semiconductor region;
- and
- a gate-electrode layer disposed on an insulation film over said channel regions and said first surface of said first semiconductor region;
- wherein said gate-electrode layer comprises first and second portions of opposite conductivity type, each one of the first portions extending across a first surface portion of said first semiconductor region, between a first region over a first channel region and a second region over a neighboring second channel region.
A metal-oxide-semiconductor device comprising:
- a first semiconductor region of a first conductive type having a first surface and a second surface;
- a plurality of second regions of a second conductive type at said first surface of said first semiconductor region, said second regions being substantially rectangular in shape;
- a third region of said first conductive type in each of said second regions;
- a plurality of channel regions formed between said third region and said first surface of said first semiconductor region;
- and
- a gate-electrode layer disposed on an insulation film over said channel regions and first surface portions of said first semiconductor region;
- wherein portions of said gate-electrode layer disposed over two adjacent channel regions and interposing first-surface portions of said first semiconductor region having a conductivity type opposite to the conductivity type of other portions of the gate-electrode layer, portions of the gate-electrode layer not disposed over said channel regions and interposing first-surface portions of said first semiconductor region are formed by ion implantation at a dose of 10.sup.11 to 10.sup.13 /cm.sup.2, and selected portions of the gate-electrode layer disposed over selected first-surface portions of said first semiconductor region, which surface portions are interposed between longer sides of two adjacent second regions, have a conductivity type opposite to the conductivity type of portions of the gate-electrode layer disposed over said channel regions along longer edge of said channel regions.
Dependencies are inferred from the claim text.