DRAM cells having stacked capacitors of fin structures and method of making thereof

A method of making a DRAM cell having stacked capacitors, comprising the steps of:

• (a) defining field regions and active regions on a semiconductor substrate and forming gates on the field regions and the active regions;
• (b) forming side wall oxide layers on the sides of the gates and forming source and drain regions on the substrate;
• (c) depositing a first silicon dioxide layer on the overall exposed surface;
• (d) depositing a silicon nitride layer on the first silicon dioxide layer, wherein the silicon nitride layer has a thickness greater than the thickness of the first silicon dioxide layer;
• (e) depositing a second silicon dioxide layer on the silicon nitride layer, wherein the second silicon dioxide layer has a thickness greater than the thickness of the first silicon dioxide layer;
• (f) etching the second silicon dioxide layer at portions thereof corresponding to buried contact regions;
• (g) wet etching the silicon nitride layer using the remaining portions of the second silicon dioxide layer as a mask, wherein portions of the silicon nitride layer disposed beneath the second silicon dioxide layer are removed to form an open volume beneath the second silicon dioxide layer;
• (h) etching the first silicon dioxide layer at the buried contact regions;
• (i) depositing a polysilicon layer on the overall exposed surface, wherein polysilicon is deposited in the open volume beneath the second silicon dioxide layer;
• (j) etching the polysilicon layer to form storage nodes of the stacked capacitors;
• (k) etching the second silicon dioxide layer and the silicon nitride layer;
• and
• (l) forming a dielectric layer and plate nodes of the stacked capacitors.

A method for forming a capacitor on a semiconductor substrate comprising the steps of:

• (a) forming a first insulation layer on the semiconductor substrate;
• (b) forming a second insulation layer on the first insulation layer;
• (c) forming a third insulation layer on the second insulation layer;
• (d) etching portions of the third insulation layer;
• (e) wet etching portions of the second insulation layer, wherein portions of the second insulation layer beneath the third insulation layer are removed to form an undercut region;
• (f) etching the first insulation layer to form a contact with the semiconductor substrate;
• (g) forming a polysilicon layer on the overall surface, wherein polysilicon fills at least a portion of the undercut region;
• (h) patterning the polysilicon layer to form an electrode of the capacitor;
• (i) removing remaining portions of the third and second insulation layers;
• (j) forming a dielectric layer on the polysilicon layer;
• and
• (k) forming a plate electrode on the dielectric layer.