Method of manufacturing semiconductor devices having a resist patern coincident with gate electrode

A method of manufacturing a CMOS semiconductor device having a source region, a gate region, a drain region, and a substrate connecting region with a channel length of at most 0.5 .mu.m, comprising the steps of:

• forming a gate oxide film having a film thickness of at most 120 .ANG. over a substrate;
• forming a gate material film over the gate oxide film;
• forming a first resist pattern coincident with a shape of a gate over the gate material film;
• hardening the first resist pattern by irradiating with ultraviolet rays;
• forming the gate region by etching the gate material film by using the first resist pattern as a mask;
• forming a second resist pattern to cover the substrate connecting region, the second resist pattern having openings respectively defining the gate region, the source region, and the drain region prior to removal of the first resist pattern;
• implanting impurities into portions of the substrate corresponding to the source region and the drain region by using the first resist pattern and the second resist pattern as a mask, the first resist pattern inhibiting the impurities from penetrating the gate region;
• removing the first and the second resist patterns;
• and
• performing an annealing heat treatment to activate the impurities.