Bank erasable, flash-EPROM memory
AssigneeSGS-Thomson Microelectronics S.A.
InventorsVirginia Natale, Gianluca Petrosino, Flavio Scarra
Life of this patent
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Abstract
Each common source region of the cells of a row of a FLASH-EPROM matrix may be segmented and each segment is individually connected to a secondary source line patterned in a second level metal layer by a plurality of contacts between each common source region and patterned portions of a first level metal and through as many interconnection vias between the latter patterned portions of the first level of metal and the relative secondary source line patterned in the second metal layer. The secondary source lines are brought out of the matrix orthogonally to the bit lines and may be connected to a dedicated selection circuitry, thus permitting the erasing by groups or banks of cells of the FLASH-EPROM memory.
Claims20
A FLASH-EPROM memory formed by a plurality of unit memory cells integrated in a semiconductor substrate, each cell having a drain region, a gate structure and a source region, the cells being organized in a matrix of rows and columns being individually addressable through a first family of individually selectable parallel conducting lines word lines and a second family of individually selectable parallel conducting lines (bit lines), patterned in a first level metal layer disposed on a first isolating dielectric layer, each word line being part of said gate structure of the cells aligned along a certain row and each bit line being connected through contacts formed through said first isolating dielectric layer to a drain region of the cells aligned along a certain column, the memory cells being erasable as a group by application of an erasing voltage to common source regions formed in said semiconducting substrate;
- characterized by comprising:
- a third family of individually selectable parallel conducting lines (SECONDARY SOURCE LINES) and patterned in a second level metal layer disposed over a second insulating dielectric layer laying over said conducting lines of said second family (bit lines);
- each SECONDARY SOURCE LINE of said third family of lines being connected to a common source region of the unit memory cells belonging to a certain row between said common source region through at least a contact and a patterned portion of said first level metal layer and an interconnection via between said patterned portion and said conducting line, thus permitting the erasing of groups of unit cells of said matrix sharing a common source region through a selected conducting SECONDARY SOURCE LINE of said third family of lines.
A FLASH-EPROM memory formed by a plurality of unit memory cells integrated in a semiconductor substrate, each cell having a drain region, a gate structure and a source region, the cells being organized in a matrix of rows and columns and being individually addressable through a first family of individually selectable parallel conducting lines word lines and a second family of individually selectable parallel conducting lines (bit lines) patterned in a first level metal layer disposed on an isolating dielectric layer, each line word line of said first family of lines being part of said gate structure of the cells aligned along a certain row and each bit line being connected through contacts formed through said isolating dielectric layer to a drain region of the cells aligned along a certain column, the memory cells being erasable as a group by application of an erasing voltage to common source regions formed in said semiconducting substrate, characterized by comprising:
- a third family of parallel, segmented, source contact lines, patterned in the same metal layer of first level, running parallel in the same metal layer of first level, running parallel to and alternately with a plurality of parallel lines of second family (bit lines);
- each segment of said segmented source contact lines being connected to a common source region of unit cells disposed along a certain row of the matrix by means of at least a contact formed through said isolating dielectric layer;
- a fourth family of individually selectable parallel conducting source interconnection lines, patterned in the same metal layer of first level, each orthogonally crossing and connecting in common a plurality of aligned segments of said source contact lines and orthogonally crossing said conducting lines of said second family (bit lines) in interruption zones thereof;
- electrical continuity of each of said lines belonging to said second family of lines (bit lines) in the interruption zones with each of said source interconnection lines being realized by means of an electrical underpath through a patterned portion of an existing conducting layer, in which said conducting lines of said first level word lines are patterned;
- the cells of said memory matrix being erasable by groups, showing a common connected source region, through a selected source interconnection line of said fourth family of lines.
A FLASH-EPROM memory array formed by a plurality of memory cells, comprising:
- a plurality of drain regions formed in a substrate for respective memory cells within said array;
- a plurality of distinct source regions formed in said substrate and adjacent respective drain region, each said source regions being physical common to a plurality of memory cells;
- channel regions in said substrate between said respective drain regions and said source regions;
- floating gates overlying said substrate over said channel regions and being separate by a dielectric layer from said substrate;
- control gates overlying respective floating gates;
- a plurality of distinct source contact lines, each electrically coupled to respective distinct source regions so that each distinct source region is electrically isolable from other distinct source regions for attaching one of said distinct source regions to a voltage potential different from other source regions;
- and
- selection circuitry coupled to said source contact lines for applying a desired voltage potential to selected, distinct source contact lines.
A FLASH-EPROM memory array formed by a plurality of memory cells, comprising:
- a plurality of drain regions formed in a substrate for respective memory cells within said array;
- a plurality of partitioned source diffusions formed in said substrate and adjacent respective drain regions, each of said partitioned source diffusions forming a plurality of distinct source regions;
- channel regions in said substrate between said respective drain regions and the distinct source regions;
- floating gates overlying said substrate over said channel regions and being separate by a dielectric layer from said substrate;
- control gates overlying respective floating gates;
- a plurality of distinct source contact lines electrically coupled to the source regions so that each distinct source region is electrically isolable from other distinct source regions for attaching said source regions to a desired voltage potential;
- and
- selection circuitry coupled to said source contact lines for applying the desired voltage potential to selected, distinct source contact lines.
Dependencies are inferred from the claim text.