Compensating lead structure for distributed IC components

An integrated circuit (IC) constructed using exposure and etching steps in an IC fabrication process, said IC having an electrical lead structure coupled to a distributed electrical component having distributed electrical component elements coupled in a distribute circuit, comprising:

• said electrical lead structure comprising an etchable conductive layer constructed in a configuration with graduated coupling widths forming a graduated range of respective etchable dimensions arranged in an electrically coupled sequence from a widest coupling width to a narrowest coupling width;
• said lead structure having a primary lead at a first end of the electrically coupled sequence of graduated coupling widths adjacent to the widest coupling width, and a plurality of secondary leads distributed along the electrically coupled sequence of graduated coupling widths and being coupled respectively to the distributed electrical component elements of the distributed electrical component;
• said graduated coupling widths of the lead structure electrically coupling the secondary leads to the primary lead of the electrical lead structure through respective incremental portions of the electrically coupled sequence of graduated coupling widths of the electrical lead structure;
• said electrical lead structure being oriented to compensate for IC fabrication process variation in exposure and etching steps by varying the number of distributed electrical component elements electrically coupled into the distributed circuit.

A distributed CMOS transistor structure having a plurality of NMOS transistor elements coupled in parallel and a plurality of PMOS transistor elements coupled in parallel, said NMOS and PMOS transistor elements each having a source region, a drain region and an etchalbe conductive layer gate segment, said gate segments of the NMOS and PMOS transistor elements being coupled together to form an input of the CMOS transistor structure, said drain regions of the NMOS and PMOS transistor elements being coupled together to form an output of the CMOS transistor structure, the improvement comprising:

• a first source lead structure comprising an etchable conductive layer constructed in a configuration with graduated coupling widths forming a graduated range of respective etchable dimensions arranged in an electrically coupled sequence;
• said first source lead structure having a primary lead coupled to a first power rail and a plurality of secondary leads coupled respectively to source regions of the PMOS transistor elements, said graduated coupling widths of the first source lead structure coupling the secondary leads to the primary lead of the first source lead structure through respective incremental portions of the electrically coupled sequence of the graduated coupling widths;
• and a second source lead structure having a primary lead coupled to a second power rail and a plurality of secondary leads coupled respectively to source regions of the NMOS transistor elements, said second source lead structure having graduated coupling widths coupling the secondary leads to the primary lead of the second source lead structure through respective incremental portions of the electrically coupled sequence of the graduated coupling widths;
• said first and second source lead structures being oriented to compensate for IC fabrication process variation in length of the etchable conductive layer gate segments by varying the number of distributed NMOS and PMOS transistor elements coupled in the distributed circuit of the CMOS transistor structure.

An integrated circuit constructed using exposure and etching steps in an IC fabrication process, said IC having an electrical lead structure coupled to a distributed input resistor having distributed electrical resistor elements, said input resistor being coupled to the control gate node of an MOS input transistor, comprising:

• said electrical lead structure comprising an etchable conductive layer constructed in a configuration with graduated coupling widths forming a graduated range of respective etchable dimensions arranged in an electrically coupled sequence from a widest coupling width to a narrowest coupling width;
• said lead structure having a primary lead at a first end of the electrically coupled sequence of graduated coupling widths, and a plurality of secondary leads distributed along the electrically coupled sequence of graduated coupling widths and being coupled respectively to the distributed electrical resistor elements of the distributed input resistor;
• said graduated coupling widths of the lead structure coupling the secondary leads to the primary lead of the electrical lead structure through respective incremental portions of the electrically coupled sequence of graduated coupling widths;
• said electrical lead structure being oriented to compensate for IC fabrication process variation in exposure and etching steps by varying the number of distributed electrical resistor elements in the distributed input resistor.

A method of compensating for a first variation in an electrical operating parameter of an IC device caused by uncontrolled process variation in exposure and etching steps during fabrication of the IC device comprising:

• coupling an etchable electrical lead structure to a distributed IC electrical component;
• constructing the electrical lead structure form an etchable conductive layer in a configuration with graduated etchable coupling widths and coupling the respective graduated etchable coupling widths to respective distributed electrical component elements of the distributed IC electrical component;
• conducting the electrical lead structure to cause a second variation in said electrical operating parameter of the IC device in response to said uncontrolled process variation by varying the number of distributed electrical component element sin the distributed IC electrical component;
• and exposing and etching the electrical lead structure during fabrication of the IC device so that the second variation of the electrical operating parameter varies in a parameter value direction opposite the first variation for process compensation.