Structure of a semiconductor chip having a conductive layer

A conductive layer structure of a semiconductor integrated circuit device comprising:

• a semiconductor substrate having a major surface, said semiconductor substrate having a center point of the major surface;
• a lower conductive layer formed on the major surface of said semiconductor substrate, said lower conductive layer including a first wiring line extending lengthwise in a first direction and widthwise in a second direction substantially perpendicular to the first direction;
• an insulating layer formed on said lower conductive layer;
• an upper metal conductive layer formed on said insulating layer, said upper metal conductive layer including a second wiring line extending lengthwise in the second direction and widthwise in the first direction, the width of the second wiring line being larger than the width of the first wiring line, the first and second wiring lines intersecting at a crossing area which has an inner boundary extending in the second direction,
• the second wiring line having a slit which is located at a region where a straight line passing through the center point of said semiconductor substrate and the inner boundary of the crossing area of the first and second wiring lines is passed, the slit being not located in the crossing area of the first and second wiring lines;
• and
• a passivation film formed on said upper metal conductive layer.

A conductive layer structure of a semiconductor integrated circuit device comprising:

• a semiconductor substrate having a major surface;
• a lower conductive layer formed on the major surface of said semiconductor substrate, said lower conductive layer including a first wiring line extending lengthwise in a first direction;
• an insulating layer formed on said lower conductive layer;
• an upper metal conductive layer formed on said insulating layer, said upper metal conductive layer including a plurality of second wiring lines extending lengthwise in a second direction substantially perpendicular to the first direction, the second wiring lines being arranged in parallel to each other and each having a width in the first direction smaller than about 40 .mu.m, the second wiring lines receiving a same signal;
• and
• a passivation film formed on said upper metal conductive layer.