Method of making dynamic random access memory having a reliable contact

A method for producing a dynamic random access memory on a substrate, said substrate being defined with a memory cell region formed with memory cell transistors and a sense amplifier region formed with sense amplifiers, said method comprising the steps of:

• providing a first insulation layer on said substrate including the memory cell region and the sense amplifier region to bury the memory cell transistors and the sense amplifiers underneath;
• providing a spacer layer having a composition different from the first insulation layer on said first insulation layer;
• exposing a drain region of the memory cell transistor by providing a contact hole through the spacer layer and through the first insulation layer;
• depositing a first conductor layer on said spacer layer such that said first conductor layer covers the exposed drain region of the memory cell transistor and a side wall of the contact hole;
• patterning the first conductor layer to form a first electrode of a memory cell capacitor;
• removing the spacer layer selectively against the underlying first insulation layer by etching to form a space under the first electrode;
• depositing a dielectric film on an exposed surface of the first electrode;
• depositing a second conductor layer on said first insulation layer including the first electrode that is covered by the dielectric film, said second conductor layer being deposited also on the first insulation layer covering the sense amplifier region;
• patterning the second conductor layer to form a second electrode that opposes the first electrode of the memory cell capacitor with the dielectric film intervening therebetween;
• said step of patterning including a step of patterning the second conductor layer to leave a conductor pattern on the first insulation layer covering the sense amplifier region in correspondence to a part having a depressed upper major surface;
• depositing a second insulation layer on said first insulation layer covering the memory cell region and the sense amplifier region to bury the memory cell capacitors on the memory cell region and the conductor pattern on the sense amplifier region underneath an upper major surface of the second insulation layer;
• providing an interconnection pattern on the upper major surface of the second insulation layer in correspondence to a part of the sense amplifier region where the conductor pattern is formed;
• providing a spin-on-glass layer on the upper major surface of the second insulation layer to fill a depression formed on the upper major surface of the second insulation layer by the interconnection pattern, said spin-on-glass layer having an upper major surface and being provided to expose an upper major surface of the interconnection pattern above the upper major surface of the spin-on-glass layer;
• providing a third insulation layer on the upper major surface of the spin-on-glass layer to cover both the memory cell region and the sense amplifier region, said third insulation layer being provided to bury the interconnection pattern underneath;
• providing a contact hole through the third insulation layer in correspondence to the conductor pattern to expose an upper major surface of the conductor pattern;
• and
• providing an interconnection pattern on the upper major surface of the third insulation layer in contact with the conductor pattern via the contact hole.