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US 5,281,865 AGranted
Flip-flop circuit
AssigneeHitachi, Ltd.
InventorsHiroki Yamashita, Hiroyuki Itoh, Hirotoshi Tanaka, Atsumi Kawata, Kenji Nagai, Kazuhiro Yoshihara, Ichiro Imaizumi
Life of this patent
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Abstract
A flip-flop circuit receives a pair of complementary data signals, then outputs complementary signals corresponding to the pair of complementary data signals. The pair of data signals are also supplied to a driving gate means which outputs a signal corresponding to at least one data signal of the pair of data signals supplied thereto. The driving gate means also comprises at least one try-state gate controlled by a clock signal. An output signal of the driving gate means is held by a memory means, and also outputted as complementary output signals.
Claims30
A flip-flop circuit comprising:
- driving gate means for receiving a pair of complementary data signals and outputting a single phase data signal indicative of said complementary data signals;
- and
- memory means, connected to a first output node of said driving gate means, for holding the output signal of said driving gate means and outputting a pair of complementary signals indicative of said pair of complementary data signals, respectively,
- wherein said driving gate means includes a first tri-state gate having inputs for receiving said pair of complementary data signals and responding thereto, in response to a clock signal, for providing said single phase data signal to said first output node, and
- wherein said first tri-state gate comprises:
- a first NOR gate for receiving at a first input thereof a first one of said pair of complementary data signals and at a second input thereof said clock signal,
- a second NOR gate for receiving at a first input thereof the second one of said pair of complementary data signals and at a second input thereof said clock signal,
- a first normally-off type FET, a gate of which is connected to an output of said first NOR gate and a drain of which is connected to a first power source terminal, and
- a second normally-off type FET, a gate of which is connected to an output of said second NOR gate, a drain of which is commonly connected with a source of said first normally-off type FET to said first output node of said driving gate means and a source of which is connected to a second power source terminal.
6 more elements
A flip-flop circuit comprising:
- driving gate means for receiving a pair of complementary data signals and outputting a single phase data signal indicative of said complementary data signals, wherein said driving gate means includes a first tri-state gate having inputs for receiving said pair of complementary data signals and responding thereto, in response to a clock signal, for providing said single phase data signal to said first output node;
- memory means, connected to a first node of said driving gate means, for holding the output signal of said driving gate means and outputting a pair of complementary signals indicative of said pair of complementary data signals, respectively;
- a second driving gate means coupled to receive the pair of complementary signals outputted from said memory means and providing a second single phase output signal at a second output node of a level indicative to the pair of complementary signals received from said memory means
- wherein said second driving gate means includes a second tri-state gate having inputs for receiving the pair of complementary signals from said memory means and outputting said second single phase signal in response to a phase complement of said clock signal;
- and
- a second memory means, connected to said second output node of said second driving gate means, holding a previously attained said second output signal at said second output node when said second tri-state is in a high impedance state and outputting a pair of complementary signals corresponding to said pair of complementary data signals.
3 more elements
A flip-flop circuit comprising:
- a pair of input terminals for inputting a pair of complementary signals;
- first and second output terminals for outputting complementary signals corresponding to the pair of complementary input signals;
- first, second, third and fourth NOR gates, each having first and second inputs and an output,
- wherein the first of said first and fourth NOR gates are coupled to receive a clock signal and the second inputs of which are connected to one input terminal of said pair of input terminals, respectively, and
- wherein the first inputs of said second and third NOR gates are coupled to receive said clock signal and the second inputs of which are connected to the other input terminal of said pair of input terminals;
- a first FET, a gate of which is connected to an output node of the first NOR gate, a drain of which is connected to a first power source terminal, and a source of which is connected to said first output terminal;
- a second FET, a gate of which is connected to an output node of said second NOR gate, a drain of which is connected to said first output terminal, and a source of which is connected to a second power source terminal;
- a third FET, a gate of which is connected to an output node of said third NOR gate, a drain of which is connected to said first power source terminal, and a source of which is connected to said second output terminal;
- a fourth FET, a gate of which is connected to an output node of said fourth NOR gate, a drain of which is connected to said second output terminal;
- and
- a pair of inverters, a first one of which has an input and output connected to said first and second output terminals, respectively, and the second one of which has an input and output connected to said second and first output terminals, respectively.
8 more elements
A flip-flop circuit comprising:
- a first tri-state gate having inputs for receiving a pair of complementary data signals and, in response to a first clock signal, providing a single phase output signal indicative of said complementary data signals;
- an inverter having an input coupled to receive the output signal of said first tri-state gate and having an output for providing a phase complement signal of said output signal;
- and
- a second tri-state gate, an output node of which is connected to an output node of said first tri-state gate and inputs of which are coupled to receive the output signal of said first tri-state gate and the phase complement output signal from said inverter, for outputting a signal to hold an output voltage of said first tri-state gate in response to a second clock signal, complementary to said first clock signal.
1 more element
Dependencies are inferred from the claim text.