Optical-input latch-circuit cell array

An optical-input cell used for an optical-input section in a processor chip which includes a plurality of processor units wherein each of said plurality of processor units includes a processing section and wherein said optical-input section has an array of optical-input cell elements which are arranged in a two-dimensional array, each said optical-input cell element comprising:

• a light-detecting element generating an output signal;
• a differential amplifier circuit comprising first and second operating transistors, a differential transistor pair connected to said first and second operating transistors, and a latch switch connected to said differential transistor pair, said second operating transistor having an output terminal at which a negative feedback signal is provided;
• a first control-voltage generating circuit for generating a first control voltage for said first operating transistor to which the output signal of said light-detecting element is applied;
• and
• a second control-voltage generating circuit for generating a second control voltage for said second operating transistor, said second control voltage being different from said first control voltage by a predetermined voltage, and being provided through negative feedback from the output terminal of said second operating transistor;
• said first control-voltage generating circuit being complementary to said second control-voltage generating circuit,
• said latch switch being turned on and off in synchronism with a control clock signal in said processor unit,
• wherein an optical-input signal which is applied to said light-detecting element to produce the output signal which is latched and amplified in order to output a digital electrical signal from said differential amplifier circuit which digital electrical signal is applied to an input gate of one of said processing sections.

An optical latch circuit used for an optical-input section of a processor chip which includes a plurality of processor units wherein each of said plurality of processor units includes a processing section and wherein said optical-input section has an array of said optical latch circuits which are arranged in a matrix, each said optical latch circuit comprising:

• a light-detecting element;
• a differential amplifier circuit having a first CMOS circuit, a second CMOS circuit, and a NMOS latch switch connected to said first CMOS circuit and said second CMOS circuit;
• an optical-output stabilizing circuit for generating a first control voltage on a control gate of a PMOS transistor included in said first CMOS circuit to which a voltage generated by said light-detecting element is applied;
• and
• an auto-zero negative feedback circuit for generating a second control voltage, which is different from said first control voltage by a predetermined voltage, on a control gate of a PMOS transistor included in said second CMOS circuit through a negative feedback circuit coupled to an output terminal of said PMOS transistor included in said second CMOS circuit;
• said optical-output stabilizing circuit being complementary to said auto-zero negative feedback circuit,
• said latch switch being turned on and off in synchronism with a control clock signal provided by said processor unit,
• wherein, when an optical-input signal is applied to said light-detecting element it is latched and amplified to produce a digital electrical signal at an output terminal of said differential amplifier circuit.

An optical-input cell in which a plurality of optical-input cell elements are arranged in a two-dimensional array, each said optical-input cell element comprising:

• a light-detecting element;
• a differential amplifier circuit having a first CMOS circuit, a second CMOS circuit and a NMOS latch switch connected to said first CMOS circuit and said second CMOS circuit;
• an optical-output stabilizing circuit which generates a first control voltage on a control gate of a PMOS transistor included in said first CMOS circuit to which a voltage generated by said light-detecting element is applied;
• and
• an auto-zero negative feedback circuit which generates a second control voltage, that is different from said first control voltage by a predetermined voltage, on a control gate of a PMOS transistor included in said second CMOS circuit through a negative feedback circuit coupled to an output terminal of said PMOS transistor included in said second CMOS circuit;
• said optical-output stabilizing circuit being complementary to said auto-zero negative feedback circuit.